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Modification of HDL reference design for FMCDAQ2 running on Zynq

Question asked by damchanhung on Oct 20, 2016
Latest reply on Dec 30, 2016 by rejeesh



I have some queries on HDL reference design for FMCDAQ2 running on Zynq.


I would like to do the following.


Option 1:


TX: 4.9152 Gbps

RX: 3.6864 Gbps


Option 2:


TX: 7.3728 Gbps

RX: 3.6864 Gbps


I noticed that the PHY is util_jesd_gt and axi_jesd_gt is not part of Xilinx JESD204B PHY reference design which allows one to change for different line rate.

For the case of this PHY provided by Analog Devices, the PHY seems to be fixed at line rate of 10Gbps, transmit, receive.


Is it possible to provide some advise on how to modify the util_jesd_gt and axi_jesd_gt IP to achieve the line rates discussed above?

Or is it just changing of software?


Thank you,