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Query in AD9371 Evaluation Board  VCXO selection doc

Question asked by sripad Employee on Oct 21, 2016
Latest reply on Oct 21, 2016 by Vinod

With reference to


From the AD9528 data sheet: 

M1 = 3,4,5

Also it appears from the diagrams Figs 27 & 30 that the x 2 multiplier is in series with the 5 bit divider. it appears (Table 50) that this can be enabled with any value of R1 divider, If this is true then additional dividers possible are:

0.5, 1.5, ... 15.5 

Finally, regarding the requirement 

Maximum frequency after the RF VCO divider (M1) is limited to 1000MHz

I don't find any such limitation in the data sheet. I do see (Table 8)

Output Frequency 1000MHz or 1250MHz otuputs 1 and 2 only

However output is after channel divider. is it possible that the channel divider will work with input < 1250MHz 


Please verify