I have designed an I2S receiver in my Altera Cyclone III FPGA using the configuration shown in the I2S specification (attached alongside), fig. 7, page 7.
The configuration shown is for only 1 data line. However in the case of ADV7842, it can use upto 4 I2S data lines. So, I would have to design 4 sets of receiver configurations with common SCLK and WS (LRCLK in ADI terms). Am I right ?
Also each data line (I2S0 to I2S3) exactly denotes what? It carries audio data for each speaker pair, right?
Working on audio processing for the first time. So, lot's of areas that are unknown to me.