I have test sending data via DMA and find its time delay is not accurate because my custom data time is strict, especially on delay time. I also want to capture data immediately when i send tx data because i need phase information. So I want to insert my data ROM core into the hdl project.
I use 2 ROMs. A ROM has a 16 bit bus for dac_data_i0, a rom has a 16 bit bus for dac_data_q0. the memory read enable / is connected to dac_valid_*. The read clock should be connected to l_clk. I also creat 3 port:Rom_cnt connect Rom_addr, ROM_rst_connect Rom rst and l_clk connect l_clk. I use l_clk and Rom_cnt to generate addr, use rst for reset the ROM. I disconnect the dac_data_i1/q1,dac_valid_i1/q1 and dac dunf with DMA, am i right? I plan send 50 us data and reset 50 us, But it is only 12.5 us! That is mean l_clk is 4* data_clk? Could anyone help me?