AnsweredAssumed Answered

Clock Out frequencies not as expected.

Question asked by Mike4fpgas on Oct 20, 2016
Latest reply on Oct 20, 2016 by Mike4fpgas

I am using the AD9371 Transceiver Evaluation Software to create the structures to program the AD9528 and AD9371 on a Mykonos board. We are using the on-board OCXO at 122.88MHz but need the output frequencies to the AD9371 and to the FPGA to be 153.6MHz.

I entered the parameters as follows:

 

Transceiver options

However, the resulting structure is as follows:

ad9528outputSettings_t clockOutputSettings =
{
 53237,
    {0,0,0,2,0,0,0,0,0,0,0,0,2,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
    {122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000}

 

I interpret this as the output clocks are 122.88MHz rather than the requested 122.88MHz. I expect it to divide by 8 to get the 153.6MHz rather than dived by 10.

 

The structure for the input clock for the AD9371 is correct at 153.6MHz:

static mykonosDigClocks_t mykonosClocks =
{
    153600,         /* CLKPLL and device reference clock frequency in kHz*/
    6144000,        /* CLKPLL VCO frequency in kHz*/
    VCODIV_1,       /* CLKPLL VCO divider*/
    4               /* CLKPLL high speed clock divider*/
};

 

Am I interpreting something wrong or is this a bug in the program?

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