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ad9361 sync_in

Question asked by lesley on Oct 20, 2016
Latest reply on Oct 20, 2016 by Vinod
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Hi all,

      I am confused about how sync_in pulse works in the ad9361 design.

      If I use two fmcomms3 board, and the external clock fed to both of them is a common reference source which means the reference clock of BBPLL in both devices are in the same frequence and same phase. Since the BBPLLs in devices are same, I think the data_clk they output should also be in the same frequency and phase. If it's correct, why do we need to send two sync_in pulses from FPGA, and if there's something wrong with my opinion, please help me figure it out and explain how sync_in pulse works in detail.