I am interested in using the AD9371 with the full Rx and Tx bandwidths of 100MHz. What are the acceptable DEV_CLK speeds that the AD9371 can accept in order to operate at these bandwidths?
On acceptable device clocks. The input to the PFD of the PLL needs to be between 10MHz to 80MHz. there is a scaler between the PFD and device clock input that can scale by a factor of 2, 1, 1/2, 1/4. We allow a range from 10MHz to 320MHz as the device clock. For example if we apply a device clock of 320MHz this would be scaled by 1/4 and the input to clock frequency to the PFD would be 80MHz. The CLKPLL operates in integer mode so we would then be able to generate IQ rates of multiples of 80MHz. So for this reason the GUI allows the choice of IQ rate first and then supplies the allowable choices of device clock. The actual range of device clock though is from 10MHz to 320MHz but the value you choose within this range will depend on the desired IQ rates.
For Example , for TX BW of 100 MHz, sample rate should be > 300 MHz. For Sample rate of 307.6 MHz and BW of 100 MHz Device clocks supported by GUI are 307.2 , 153.6, 76.8 and 38.4 MHz
The frequency range of the DEV_CLK signal must be between 10 MHz and 320 MHz. The maximum voltage level for the DEV_CLK signal is 2.0 V p-p differential, and the minimum input level is 300 mV p-p differential.
For specific datarates and bandwidth you can use the profile generator to find the supported DEV_CLK.
Typically all systems will have AD9528 , the clock generation and distribution chip which can take any reference and generate the required Ref_Clk as described in UG-992 figure 53. AD9528 also generates Sysref and Sync signals required for JESD synchronization.
If you have an Evaluation board and MTES GUI , you can see currently supported Device clocks for different datarate/ Bandwidth.
That is all understood and we have done that in the past. We are looking to move from the standard 30.72MHz reference. We are using the Profile/Filter Wizard to create profiles that get loaded into the MTES GUI. The problem is, not all clocks between 10MHz and 320MHz are able to be used if we want the full 100MHz bandwidths. Is there a list of acceptable DEV_CLK rates that allow for maximum Tx and Rx bandwidths of 100MHz?
For Eval board clock configuration and modification please refer.
That is helpful in setting up the AD9258 to generate a DEV_CLK, but it does not talk about acceptable DEV_CLK rates.
Is there a list of acceptable DEV_CLK rates that allow for maximum Tx primary signal BW and Rx BW of 100MHz?
Retrieving data ...