I am little confused about the INL spec. It is in terms of LSB, but they are in decimals. How is this derived? Is it saying that (for example, on figure 13) if I put a input code of 64, that the whole bit can be truncated by a little over 10% of its whole step? So, if a step size can output in increments of 20mV, then the INL tells us that the 20mV could vary by a little over 2mV for that particular step?

Hi,

Figure 12 is for the INL-R vs temperature while Figure 13 shows the DNL-R vs temperature

My understanding from your explanation is that it is the differential non-linearity(DNL) that you are describing. Let's say you have a 100kΩ potentiometer in potentiometer mode which have an LSB of about 390Ω. For code 64, the expected output resistance is about 25kΩ which can vary by ±1 LSB max. This is about ±390 Ω which will give you a value from 24.61 kΩ to 25.39 kΩ.

Note that you will still have to take the 20% resistor tolerance in your computation.

Regards,

Mark