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about the usage of GPIO in AD9371

Question asked by JunHu on Oct 19, 2016
Latest reply on Jan 3, 2017 by Vinod

Dear all,

 

I have some questions for the GPIO usage,

 

1. I saw UG-992, chapter 'AD9371 transceiver evaluation software (TES) --> GPIO configuration Tab', figure 166/167 describes how to configure GPIO pin. I am just wondering:

  • a) in figure 166, PIN0~1, 3~8 have been configured as INPUT, but in figure 167, PIN0~8 have been configured as OUTPUT, how is that possible ?? do I misunderstand it ??
  • b) is the GPIO pin configurations can only be set before 9371 starts to work (as figure 166/167 plotted) ?
  • c) during normal Rx or Tx reception and transmission, can we dynamically change its settings by certain commands (say, pre-defined pin0~pin7 is OUTPUT mode by TES, but at certain timing boundary it is changed to INPUT mode, ...) ?

 

the reason I ask this is that, we are trying to reduce the pin numbers connected to our FPGA from 9371, and it seems GPIO has a lot of pins with multiple usages (GPIO includes GPIO_x and GPIO_3p3_x, but I just focus on GPIO_x), if we can only use partial of the GPIO_x with input/output mode changing, that would be helpful.

 

2. as for the ORX path control, it is mentioned that 2 modes are supported: SPI mode and GPIO mode, and it is recommended that GPIO mode (pin control mode) is used under TDD mode.

I am wondering,  if I use SPI mode to control ORX path under TDD mode, what kind of timing latency will be suffered ??

 

thanks a lot! 

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