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What is the SPI mode for the AD7909?

Question asked by milosoftware on Oct 19, 2016
Latest reply on Oct 20, 2016 by jcolao

The datasheet says:

The CS falling edge takes the data output lines (D OUT A and
D OUT B) out of three-state and clocks out the MSB of the conver-
sion result. The rising edge of SCLK clocks all subsequent data
bits onto the serial data outputs, D OUT A and D OUT B.

I'm confused as to how to interpret this.

Does this mean that the ADC changes the outputs on the rising clock edge, so I have to read them on the falling edge? Or does this mean that the output is stable on the rising edge?

 

It also doesn't say anything about clock polarity.

 

I think it's describing SPI mode "0" here, which means that the clock is default low and data is read on the rising edge (cpol=0, cpha=0). Is that correct?

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