1) is there a VHDL (or Verilog) simulation model for AD9652 ADC?2) if not, any other sim model for parallel DDR ADC?
It would be useful for validating the FPGA design we're developing.
Unfortunately we do not have a Verilog model. Please see other thread called "AD9652 ADC tSKEW Min/Max Switching Spec" where we show plot of DCO to Data Skew along with updated specification that will be in next datasheet rev.
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