1) is there a VHDL (or Verilog) simulation model for AD9144 JESD DAC?2) if not, any other sim model for JESD DAC?
I think it'd help us validating the FPGA design we're developing.
We don't provide Verilog simulation model of AD9144. Can you use Xilinx JESD204B IP core for the simulation?
Since no simulation model of AD9144 is available, we will use Xilinx JESD204B IP core for the simulation.
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