I have several questions of the ADI reference hdl design of FMCOMMS5 +ZC706:
1、Why do you connect the "clk" pin of axi_ad9361_1 to the "l_clk" of axi_ad9361_0 in the design?
2、Are "clk" of axi_9361_0 and axi_ad9361_1 used for FPGA as data transmission clock?
If yes, why the clocks in i_tx_data and i_tx_frame module are still "l_clk" (generated from the respective data_clk transmitted from ad9361)? And why the clocks of i_rx (axi_ad9361_rx) and i_tx (axi_ad9361_tx) modules are "clk"?
3、Based on the questions above, I am wondering what's the differences and relationship between i_tx_data(i_rx_data), i_tx_frame(i_rx_frame) and i_tx(i_rx)?