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ad9361 bbpll data_clk

Question asked by lesley on Oct 18, 2016
Latest reply on Oct 20, 2016 by Vinod

Hi all,

   I have a question about the bbpll of ad9361.

   Our platform is FMCOMMS3*2+VC707. The hdl design we use refers to the ADI reference hdl design of FMCOMMS5 and we use the no-os driver code downloaded from the github.

   When we run the program, it doesn't print out the error message--Calibration Timeout (0x05E, 0x80) which indicates that the BBPLL has locked , and the message shows that both ad9361 devices are initialized correctly. However the data_clk of the slave board monitored by oscilloscope is totally in a mess while the data_clk of the master board monitored by the same way seems correct. Could you please help me analyze the reason causes the problem?