I have a question about the data_clk of ad9361. We connect two fmcomms3 with VC707 and our hdl design refer to the reference hdl of fmcomms5.
I want to check out the data_clk output of two fmcomms3, so we test the l_clk of two axi_ad9361 IP core. Because the l_clk is generated from data_clk as following:
The l_clk of the master ad9361 seems correct, however the l_clk of the slave one is totally in a mess. And if I change the slave fmcomms3 board to another one, the l_clk is still incorrect. I am quite confused. In my opinion, the data_clk is generated by the bbpll in the ad9361, so if the chip works, the data_clk(l_clk) should be good even if the timing constraints are not met. We use the no-os driver code that ADI provides and both ad9361 are successfully initialized.
Is there something wrong with my opinion? And do you guys have any idea what causes this problem?