The AD9959 device performs the IO_UPDATE based on alignment with the SYNC_CLK.
The datasheet indicates that the SYNC_CLK may vary from 2.25ns to 5.5ns with a typical value of 3.5ns relative to the REF_CLK supplied to the device.
When there are multiple AD9959 devices with a low skew <50ps distribution of REF_CLK and the SYNC_CLK is "sync'd" correctly across the devices, Can there still be a difference between the SYNC_CLK outputs ?
For example if one device is propagating at 3.5ns and another is propagating at 2.5ns there is a 1ns skew between devices even when the SYNC_CLK is "sync'd".
If they are skewed by 1ns, and the IO_UPDATE arrives with the necessary Tsu of 4.8ns on one device, but the other sees 3.8ns. Then the IO_UPDATE will occur on the next SYNC_CLK boundary on the device with the 3.8ns Tsu.
Given the variance of 2.25ns to 5.5ns then we can expect to see device to device variance across this full range. Is there a spec from Analog Devices that provides the Device to Device variation rather than absolute variation on REF_CLK to SYNC_CLK ? Based on PVT I'd expect Device to Device REF_CLK to SYNC_CLK to be much smaller value than the provided 2.25ns to 5.5ns variance, but there isn't any spec for the Device to Device REF_CLK to SYNC_CLK number.
Given an AD9959 setup with a 500Mhz system clock and 125Mhz SYNC_CLK there is a 8ns period.
But the IO_UPDATE Tsu of 4.8ns and the max variance of REF_CLK to SYNC_CLK of 3.25ns (5.5ns-2.25ns) exceeds the 8ns period. Therefore across worst case it wouldn't be possible to assure that IO_UPDATE would occur on the same SYNC_CLK boundary.
How does one assure IO_UPDATE occurs on the same SYNC_CLK rising edge given the IO_UPDATE Tsu requirement and the REF_CLK to SYNC_CLK propagation variance specification ?