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ADPD107 TIA ADC Mode Timing

Question asked by szabadaba on Oct 17, 2016
Latest reply on Oct 18, 2016 by szabadaba

I am trying to use TIA ADC Mode for the ADPD107, and the data sheet does not explicitly describe how the timing should be changed to properly sample all TIAs during a timing block. The only mention of timing with respect to TIA ADC mode is the following"

 

"To measure the response from the TIA and verify that this stage is not saturating, place the device in TIA ADC mode and slightly modify the timing. Specifically, sweep SLOTx_AFE_OFFSET until two or three of the four channels reach a minimum value (note that TIA is in an inverting configuration). All four channels do not reach this minimum value because, typically, 3 μs LED pulse widths are used and the ADC samples the four channels sequentially at 1 μs intervals. This procedure aligns the ADC sampling time with the LED pulse to measure the total amount of light falling on the photodetector (for example, background light + LED pulse)."

 

It seems like the device should be able to sample from all 4 TIAs without issue by extending the length of the LED pulse. I have been successful at making what seems like valid ADC measurements from all 4 TIAs during a timing block, but I noticed that LED pulse width, LED pulse offset, AFE width and AFE offset all have the ability to change this setup. It also appears that AFE fine offset does not have any effect in this configuration. It would be nice if there was an explicit description of how this sampling takes place so that I can optimize it, because playing around with the values leads to some confusing and non-intuitive results.

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