Is it possible to use the AD7768 DOUT interface as a SPI master and receive data for all 8 channels at 100kSPS on a DOUT0 pin? If so, could anyone please provide details on such interfacing?
There are two elements involved here, 100kSPS data output and SPI master interfacing. 100kSPS will be difficult to implement using SPI.
It is possible to output data at 100kSPS on only DOUT0. From the datasheet:
DCLK(min) = Output_data_rate x Channels_per_Dout x Nbits
DCLK(min) = 100kSPS x 8 x 32 (24 bits plus 8 bit header) = 25.6 Mbps
Therefore the minimum data clock needs to be 25.6Mbps. Since DCLK is derived from MCLK, MCLK must be in the range of 25.6MHz to 32.768MHz. (the max value) Therefore DCLK = MCLK/1
Using a 25.6MHz MCLK, there is then a choice of using Median or Fast power modes in order to achieve 100kSPS output.
The settings would be as follows: Fast power mode, decimation x 64 or Median power mode with decimation x32 depending on the power or performance needed
What is needed here is a CS signal for the SPI slave. As there is no CS signal output from the AD7768 it will be a challenge to implement such a system at 100kSPS.
If running a 25.6MHz DCLK there will be no time available between conversion results. DRDY cannot be used as the CS as the LSB of Ch7 may not get clocked in. If the device interfacing to the AD7768 can handle the 100kSPS data rate with the CS signal set constantly low, then it is possible. DRDY can be used to frame the start of the conversion result.
Another option available here would be to run the AD7768 a bit slower. If the AD7768 was set to run at 64kSPS output data rate with the maximum DCLK then there would be time available between conversions. Extra circuitry would be needed here to construct the CS signal. The CS signal could be constructed from the DRDY and DCLK signals. CS would transition low with the DRDY signal, and transition high again after 256 DCLKs have occurred.
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