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Question asked by fabrizio.fdr on Oct 15, 2016
Latest reply on Oct 21, 2016 by rbrennan


I just got a board that I designed. The Local Oscillator of the board is based on the ADF4351 (designed mainly copying from the EVAL BOARD schematic). On the Board there is an FPGA that programs the ADF4351, and the REFIN pin takes input from a 25MHz TCXO.

I started to test the Integer-Mode and everything was just fine, but when I tested the Fractional-mode I was not able to get it right. It worked just sometimes. 


Often the output was different from the desired frequency:

  • 70% of times it locked to the nearest integer frequency value (Digital Lock Detect='1')
  • 15% of times it did not lock (I could see a spectrum of some MHz around the desired frequency) (Digital Lock Detect='0')
  • 15% of times it was correctly locked (Digital Lock Detect='1')


I checked many times the register values that I was writing, I read the datasheet many times and I compared my thoughts with the ADF435x Software... Everything seamed to be right.


After hours playing with the board, by mistake, I set the LDF bit to INT-N (DB8 of REG2='1') and the output started to be always perfect.


I turned off everything and at next power up I was againin the same bad situation, no matter the  LDF setting.


I start thinking the problem could be the loop filter, but I used the exact filter used in the evaluation board.


  • Is this a common "hardware problem"?
  • Is it normal that the Digital Lock Detect says I am locked, even if I am not locked on the correct frequency?
  • Is this a matter of settings?
  • I read on the cheat sheet that the filter bandwidth is proportional to the CP current. Is it wise to try to decrease the value in order to narrow the filter bandwidth?



I thank you for the help.