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HOW TO HANDLE AD9361 and AD9364 RESET

Question asked by ViR on Oct 15, 2016
Latest reply on Oct 19, 2016 by mhennerich

What is the correct way to handle Reset for AD9361 and AD9364 ?

I am pulling up reset pin with 10K res and also reset pin is connected to FPGA through 0E.FPGA pin connected to reset have default high value.

I am facing reset issue as below:

Reading correct reg values from AD9361 and AD9364 for some time then garbage value(SPI communication).

Then when you probe reset pin to check in Oscilloscope AD9361/64 will reset then works properly till we power off.Then same cycle repeats.

I think when power is on first time AD9361/64 is not resetting properly.

Please find attached reset ckt schematics image.

Please reply ASAP.

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