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cannot build HDL adrv9371x reference design

Question asked by hgan on Oct 16, 2016
Latest reply on Nov 18, 2016 by CsomI

Hi

 

I have downloaded adrv9371x reference design, and failed to build it. Please help to take a look. Thanks in advance.

 

Windows 10 + Vivado 2016.2,  TCL scripts 

 


cd C:/hdl-dev/library/interfaces
source ./interfaces_ip.tcl
close_project
cd C:/hdl-dev/library/axi_clkgen
source ./axi_clkgen_ip.tcl
close_project
cd C:/hdl-dev/library/axi_ad9371
source ./axi_ad9371_ip.tcl
close_project
cd C:/hdl-dev/library/xilinx/axi_dacfifo
source ./axi_dacfifo_ip.tcl
close_project
cd C:/hdl-dev/library/xilinx/axi_adxcvr
source ./axi_adxcvr_ip.tcl
close_project
cd C:/hdl-dev/library/xilinx/util_adxcvr
source ./util_adxcvr_ip.tcl
close_project
cd C:/hdl-dev/library/xilinx/axi_adcfifo
source ./axi_adcfifo_ip.tcl
close_project
cd C:/hdl-dev/library/axi_dmac
source ./axi_dmac_ip.tcl
close_project
cd C:/hdl-dev/library/util_axis_resize
source ./util_axis_resize_ip.tcl
close_project
cd C:/hdl-dev/library/util_axis_fifo
source ./util_axis_fifo_ip.tcl
close_project
cd C:/hdl-dev/library/axi_hdmi_tx
source ./axi_hdmi_tx_ip.tcl
close_project
cd C:/hdl-dev/library/axi_jesd_gt
source ./axi_jesd_gt_ip.tcl
close_project
cd C:/hdl-dev/library/axi_spdif_tx
source ./axi_spdif_tx_ip.tcl
close_project
cd C:/hdl-dev/library/util_bsplit
source ./util_bsplit_ip.tcl
close_project
cd C:/hdl-dev/library/util_cpack
source ./util_cpack_ip.tcl
close_project
cd C:/hdl-dev/library/util_dacfifo
source ./util_dacfifo_ip.tcl
close_project
cd C:/hdl-dev/library/util_jesd_gt
source ./util_jesd_gt_ip.tcl
close_project
cd C:/hdl-dev/library/util_upack
source ./util_upack_ip.tcl
close_project
cd C:/hdl-dev/projects/adrv9371x/zc706
source ./system_project.tcl
close_project

 

Building Library IP's seems OK, though some INFO messages are confusing, listing as below; and source system_project log file is in the attachment.

 

axi_dacfifo
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8)" into user parameter "AXI_BYTE_WIDTH".


axi_adcfifo
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8)" into user parameter "AXI_BYTE_WIDTH".

 

util_bsplit
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 9 for port or parameter 'data_s'


util_upack
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'dac_dsf_valid_s'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'dac_dsf_sync_s'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'dac_dsf_data_s'


util_cpack
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_data_d'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_mux_enable'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_enable_s'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_valid_s'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_data_s'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_data_intlv_s'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_dsf_valid_s'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_dsf_sync_s'
INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'NUM_OF_CHANNELS_M' by 8 for port or parameter 'adc_dsf_data_s'


axi_spdif_tx
INFO: [IP_Flow 19-2228] Inferred bus interface 'S_AXIS' of definition 'xilinx.com:interface:axis:1.0'.
INFO: [IP_Flow 19-1654] Cannot find bus abstraction "xilinx.com:interface:clock_rtl:1.0" from the IP catalog.

INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'spdif_data_clk' as interface 'spdif_data_clk'.
INFO: [IP_Flow 19-1654] Cannot find bus abstraction "xilinx.com:interface:reset_rtl:1.0" from the IP catalog.


axi_jesd_gt
INFO: [IP_Flow 19-2228] Inferred bus interface 'm_axi' of definition 'xilinx.com:interface:aximm:1.0'.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-1654] Cannot find bus abstraction "xilinx.com:interface:clock_rtl:1.0" from the IP catalog.
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'qpll0_rst' as interface 'qpll0_rst'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'qpll1_rst' as interface 'qpll1_rst'.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-1654] Cannot find bus abstraction "xilinx.com:interface:reset_rtl:1.0" from the IP catalog.
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_axi': References existing address space 'm_axi'.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_axi': References existing address space 'm_axi'.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.

 

axi_dmac
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "inc_id.h" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "resp.h" from the top-level HDL file.

INFO: [IP_Flow 19-2228] Inferred bus interface 'm_dest_axi' of definition 'xilinx.com:interface:aximm:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 'm_src_axi' of definition 'xilinx.com:interface:aximm:1.0'.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-1654] Cannot find bus abstraction "xilinx.com:interface:clock_rtl:1.0" from the IP catalog.
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'm_src_axi_aresetn' as interface 'm_src_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'm_dest_axi_aresetn' as interface 'm_dest_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'm_src_axi_aclk' as interface 'm_src_axi_aclk'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_src_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_src_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_src_axi_aresetn'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'm_dest_axi_aclk' as interface 'm_dest_axi_aclk'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_dest_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 'm_dest_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'm_dest_axi_aresetn'.
INFO: [IP_Flow 19-4753] Inferred signal 'interrupt' from port 'irq' as interface 'irq'.
INFO: [IP_Flow 19-4728] Bus Interface 'irq': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 's_axis_aclk' as interface 's_axis_aclk'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'm_axis_aclk' as interface 'm_axis_aclk'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'fifo_wr_clk' as interface 'fifo_wr_clk'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'fifo_rd_clk' as interface 'fifo_rd_clk'.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-1654] Cannot find bus abstraction "xilinx.com:interface:reset_rtl:1.0" from the IP catalog.
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_dest_axi': References existing address space 'm_dest_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_src_axi': References existing address space 'm_src_axi'.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_dest_axi': References existing address space 'm_dest_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_src_axi': References existing address space 'm_src_axi'.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-1793] Cannot infer any bus interface that matches bus definition xilinx.com:interface:axis:1.0.
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_dest_axi': References existing address space 'm_dest_axi'.
INFO: [IP_Flow 19-3164] Bus Interface 'm_src_axi': References existing address space 'm_src_axi'.

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