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AD5726 reference voltages and power-up sequence

Question asked by Michael_KWE on Oct 14, 2016
Latest reply on Oct 28, 2016 by Michael_KWE

Hello support team,

 

1. The AD5726 datasheet says that the minimal negative reference voltage is -10V. On the other hand, typical application discussed throughout the datasheet utilizes +/-10V references. So it looks like the datasheet suggests working just at the lower limit of Vrefn, without any headroom. Can you comment on this?

 

2. In the power sequence section, it is recommended to apply the reference voltages after the AVss and AVdd. But in this case there will be a period of time with both Vrefp and Vrefn equal to zero, while the datasheet says Vrefp must exceed Vrefn by at least 2.5V. Is the power-up sequence an exception from this rule? Is it safe for the chip to have AVss=-15V, AVdd=+15V, and Vrefp = Vrefn = 0?

 

3. I'm considering a power-up sequence whereby the GND is always connected, then AVss and AVdd both rises linearly (but AVss at a faster rate) for 10 - 20 ms, and then both Vrefp and Vrefn are applied simultaneously. Is there anything wrong with this sequence?

 

4. I'm going to use AD688 as the reference source. Can I use pin #7 of this IC (used also for noise reduction) to turn the outputs on and off? I mean, if I connect this pin to GND via a FET, both outputs should go to zero, and return to +/-10V when the connection is removed. Is this OK?

 

Thanks in advance,

Michael 

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