Currently, I was using the AD9268-125 chip and we having data issues. I have a board with an FPGA talking to four AD9268 chips, and we noticed that some of the channel's data was junk. I figured out that the data and clock edges were happening at the same time, resulting in setup/hold time violations. I was able to fix the issue by delaying the clock with an MMCM in the Xilinx FPGA we are using.
One thing I tried was by using the AD9268 register 0x17 (DCO Output Delay) to delay the clock that way. Well it turns out that register doesn't seem to work. I tried many values and looking at the clock edge relative to data with a high speed oscilloscope, the clock was not delayed at all. I know my SPI interface is working because I'm required to set values for my set up to work, and I'm reading the values back correctly (like chip ID and chip grade registers). My setup was using a 125 MHz input clock, operating in LVDS output mode, with no clock divider set.
Has anyone else had this problem, is this a known problem with the chip? It would be nice for a datasheet errata to be released at least saying this feature may not work.