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Interleaved PPI DMA data streams to SDRAM

Question asked by Laz on Aug 22, 2011
Latest reply on Oct 11, 2011 by Prashant

According to the HRM, it should be possible to interweave the data from the two PPI ports into one memory space in SDRAM.  In my case, I want to get a large chunk of data from my FPGA into the Blackfin for additional processing.  If the even-sequence values (0, 2, 4, ...) are send over PPI0 and the odd-sequence values are sent over PPI1 (1, 3, 5, ...), I think I configure the DMA as follows:

 

DMA1_0

Source = PPI0

Dest = SDRAMBuffer

X_COUNT = 100000

X_MODIFY = 2

 

DMA1_1

Source = PPI1

Dest = SDRAMBuffer+1

X_COUNT = 100000

X_MODIFY = 2

 

Has anyone tried this?  Is it inefficient for the SDRAM?  Are the DMA FIFOs used effectively?  Am I better off just using a single PPI?

 

Any and all wisdom is appreciated.

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