Please refer to this document:
1. Table 3, bottom line (page 5) states that the glitch is typically 30 nV*s, under very different conditions:
AVDD = +5 V ± 5% or +15 V ± 5%, AVSS = −5 V ± 5% or 0 V or −15 V ± 5%, GND = 0 V, VREFP = +2.5 V or +10 V, VREFN = −2.5 V or 0 V or −10 V, RLOAD = 2 kΩ.
That is, the conditions defined for the Table 3 indicate that the glitch should be independent on power supply and reference voltages.
On the other hand, Fig. 23 (page 11) indicates that the glitch does depend on the power supply voltage.
What is the actual DAC's behavior?
2. On Fig. 23, the area under the positive part of the largest glitch (about 0.9 V peak voltage) exceeds 100 nV*ns - once again, in contradiction with Table 3. Isn't that a mistake? Can the glitch peak really reach almost 1V?
3. When you define the glitch magnitude in nV*s, do you mean to the formal integral definition (area under positive part of the glitch minus area under its negative part), or to the largest of these two areas?
Thanks in advance,