AnsweredAssumed Answered

ADV7604 EVB DSUB RGB 1080P@60Hz and 1920x1200 settings

Question asked by Sam.S on Oct 13, 2016
Latest reply on Dec 11, 2016 by Sam.S

Dear Sir,

 

I have try ADV7604 EVB for DSUB RGB analog 1080P@60Hz timing input, and output by HDMI(ADV7511) in Auto Graphic Mode settings(customer need verify ghost issue in auto graphic mode), but monitor can't  display.

 

I  have checked ADV7604 CP 0xFF BIT[4] (freerun) and ADV7511 0x9E BIT[4] (locked) , it is not in freerun for ADV7604, and ADV7511 indicate HDMI Tx have in locked status, but it still can't display.

 

My settings as below:

1080P@60Hz RGB timing:

 

writeReg = topwin.devDriver.writeReg


writeRegs = topwin.devDriver.writeRegs

 

topwin.OnReset()

writeReg(0x40, 0x0B, 0x44) # Power down ESDP block

writeReg(0x50, 0x20, 0x1F) # De-assert HDP

writeReg(0x50, 0x20, 0x0F) # Insert HDP

writeReg(0x40, 0x0C, 0x40) # Power up CP core

writeReg(0x40, 0x02, 0xF4) # OP_RANGE Enable

writeReg(0x40, 0xF6, 0xC8) # ESDP Address to C8

writeReg(0x40, 0xF7, 0x66) # DPP Address to 66

writeReg(0x40, 0xFE, 0x60) # VDP Address to 60

writeReg(0x40, 0x15, 0x90) # Disable Tristate of Pins except for Audio pins

 

writeReg(0x40, 0x00, 0x07)  #RGB Auto Graphic Mode
writeReg(0x40, 0x01, 0x02) # Pri_Mode = RGB Graphic Mode
writeReg(0x40, 0x16, 0xC8) # PLL settings 1, 148.5M/67500=2200=0x898
writeReg(0x40, 0x17, 0x98) # PLL settings 2, 148.5M/67500=2200=0x898
writeReg(0x44, 0x8F, 0x01) # FR_LL setting 1, 28.636363M/67500=424=0x1A8
writeReg(0x44, 0x90, 0xA8) # FR_LL setting 2, 28.636363M/67500=424=0x1A8
writeReg(0x44, 0xAB, 0x46) # LCOUNT_MAX setting 1, LCF=0x464
writeReg(0x44, 0xAC, 0x40) # LCOUNT_MAX setting 2, LCF=0x464
writeReg(0x44, 0x91, 0x10) # INTERLACED setting


writeReg(0x40, 0x02, 0xF2) # RGB color space
writeReg(0x40, 0x03, 0x42) # 36-bit 4:4:4 SDR mode 0

writeReg(0x40, 0x05, 0x28) # Disable AV Codes, enable Free-Run, Sync output setting
writeReg(0x40, 0x06, 0xC5) # Sync polirity setting
writeReg(0x40, 0x07, 0x54) # Sync CH1 H/V sync select

writeReg(0x40, 0x15, 0x90) # Disable Tristate of Pins except for Audio pins

writeReg(0x4C, 0x13, 0x84) # Enable the DLL on LLC (BIT[7]), and set LLC_DLL_Phase 5 bits
writeReg(0x40, 0x33, 0x40) # Muxes the DLL output on the LLC output pin (BIT[6])


writeReg(0x4C, 0x00, 0x08) # Power up ADC 0/1/2
writeReg(0x4C, 0x01, 0x06) # Power up input Mux
writeReg(0x4C, 0x02, 0x02) # ADC SW auto and Sync Select auto
writeReg(0x4C, 0x03, 0x78) # ADC 0/1 SW manual
writeReg(0x4C, 0x04, 0x90) # ADC 2/3 SW manual
writeReg(0x4C, 0x12, 0xFB) # ADC noise shaping filter controls
writeReg(0x4C, 0x13, 0x88) # LLC DLL Phase Enable, and set phase value
writeReg(0x4C, 0x0C, 0x0D) # CP core Gain controls
writeReg(0x4C, 0xA0, 0x00) # Controls for the clock divider that precedes the Video DPLL
writeReg(0x4C, 0x15, 0x00) # Sync 1/2 input selec, and no sync filter
writeReg(0x4C, 0xC8, 0x00) # phase control


writeReg(0x44, 0x85, 0x0B) # Using SSPD CH1 results, Sync Ch1 setting as separate H/V sync


writeReg(0x44, 0x3E, 0x00) # CP core pre-gain control
writeReg(0x44, 0x40, 0x80) # CP core pre-gain control
writeReg(0x44, 0x7C, 0xC0) # Polarity control for all synchronization signals output by the CP core
writeReg(0x44, 0xC3, 0x39) # CP coast control
writeReg(0x44, 0xCF, 0x00) # Macrovision controls

writeReg(0x60, 0x98, 0x88) # VDP filter adaptive slicer controls
writeReg(0x60, 0x9A, 0x00) # VDP Filter controls
writeReg(0x60, 0x9B, 0x05) # VDP filter adaptive controls
writeReg(0x60, 0x9D, 0x02) # VDP slice correction control for non standard input


writeReg(0x4C, 0xC4, 0x00) # LLC DLL Normal


writeReg(0x4C, 0x12, 0x7B) # ADI Recommended Initialization for ADCs
writeReg(0x4C, 0x0C, 0x1F) # ADI Recommended Initialization for ADCs
writeReg(0x44, 0x3E, 0x04) # ADI Recommended Initialization for ADCs
writeReg(0x44, 0xC3, 0x39) # ADI Recommendation (default value) for Graphic Mode
writeReg(0x44, 0x40, 0x5C) # ADI Recommendation (default value) for Graphic Mode

writeReg(0x44, 0x81, 0xC0)

writeReg(0x44, 0x6C, 0x10) # clamp setting 1
writeReg(0x44, 0x40, 0x5C) # gain adj
writeReg(0x44, 0xC5, 0x91) # clamp setting 2
writeReg(0x44, 0x77, 0xFF) # offset setting 1
writeReg(0x44, 0x78, 0xFF) # offset setting 2
writeReg(0x44, 0x79, 0xFF) # offset setting 3
writeReg(0x44, 0x7A, 0xFF) # offset setting 4
writeReg(0x44, 0x73, 0xF1) # gain setting 1
writeReg(0x44, 0x74, 0xCC) # gain setting 2
writeReg(0x44, 0x75, 0x6B) # gain setting 3
writeReg(0x44, 0x76, 0x1B) # gain setting 4

writeReg(0x40, 0x15, 0x00) # Enable all outputs pins

writeReg(0x50, 0x19, 0x01) # FPGA ADV7604

writeReg(0x50, 0x10, 0x05) # FPGA MUX to enable 36 bit

writeReg(0x50, 0x11, 0x08) # FPGA Video BUS A Reversal Control

writeReg(0x72, 0x01, 0x00) # Set N Value(6144)

writeReg(0x72, 0x02, 0x18) # Set N Value(6144)

writeReg(0x72, 0x03, 0x00) # Set N Value(6144)

writeReg(0x72, 0x15, 0x01) # 24 bit 422 (DDR) YCbCr input

writeReg(0x72, 0x16, 0xEC) # YPrPb 422 style3

writeReg(0x72, 0x18, 0x46) # CSC disabled

writeReg(0x72, 0x40, 0x80) # General Control packet enable

writeReg(0x72, 0x41, 0x10) # Power down control

writeReg(0x72, 0x48, 0x08) # data left justification

writeReg(0x72, 0x49, 0xA8) # Set Dither_mode - 12-to-10 bit

writeReg(0x72, 0x4C, 0x00) # 8 bit Output

writeReg(0x72, 0x55, 0x20) # Set YCrCb 422 in AVI infoframe

writeReg(0x72, 0x56, 0x08) # Set active format Aspect

writeReg(0x72, 0x96, 0x20) # HPD Interrupt clear

writeReg(0x72, 0x98, 0x03) # ADI Recommended Write

writeReg(0x72, 0x99, 0x02) # ADI Recommended Write

writeReg(0x72, 0x9C, 0x30) # PLL Filter R1 Value

writeReg(0x72, 0x9D, 0x61) # Set clock divide

writeReg(0x72, 0xA2, 0xA4) # ADI Recommended Write

writeReg(0x72, 0xA3, 0xA4) # ADI Recommended Write

writeReg(0x72, 0xAF, 0x16) # Set HDMI Mode

writeReg(0x72, 0xBA, 0xC0) # Set TX Clock Delay

writeReg(0x72, 0xDE, 0x9C) # ADI Recommended Write

writeReg(0x72, 0xE4, 0x60) # VCO_Swing_Reference_Voltage

writeReg(0x72, 0xFA, 0x7D) # Nbr of times to search for good phase

topwin.ReadCurrentInterface()

 

Would you please help me to verify my settings?

 

Thank you very much.

 

Regards,

Sam

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