I wonder if there are any details on the used interpolation / decimation filters in the FIR accelerator of the ADSP21469 (and similar processors).
Secondly, if I input a sine wave into a decimation / interpolation sequence with the same down/upsampling factor, what will be the difference between the input and output signal? Let us assume that the filter passed to the accelerator does not influence amplitude and phase.
Example: fs,input = 48 kHz, decimation by factor 8, interpolation by factor 8. Sine wave at f=100 Hz.
Lastly, is it possible to implement a filter at a reduced sampling rate with upsampling to the original sampling rate in one pass of the accelerator by chaining?