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AD9361 (Catalina) receive path problem in TDD mode

Question asked by Jon.Kraft Employee on Oct 12, 2016
Latest reply on Oct 13, 2016 by Vinod

I'm developing a system where in TDD mode the Catalina TDD mode isn't used.  Instead, the Catalina is essentially in FDD mode where the Tx/Rx synthesizers aren't powered down during the Rx/Tx (opposite) time periods. Control of the Tx and Rx switches and amplifiers are done external to Catalina via the FPGA.


But looking at the receive I/Q samples, we noticed what looks like LO suppression being messed up resulting in a DC offset primarily in Q but sometimes in I.

Is there something that we have missed by programming the Catalina to FDD mode but using it in TDD mode that won't work? One thought, is there a way to trigger a fast LO suppression calibration by either GPIO or SPI commands?