AnsweredAssumed Answered

ADRV9371 HDL Reference Design : Building projects manually on Vivado is not working

Question asked by amdakwar12 on Oct 13, 2016
Latest reply on Oct 19, 2016 by CsomI

Hi,

 

I am trying to build ADRV9371 HDL ref. Design Project manually on Xilinx vivado 2016.2.

I have tried with  hdl-dev, hdl-dev_ad5766 and hdl-dev_zybo branches available on GITHUB page.

But I am getting this error when I execute source ./ system_project.tcl command

 

## p_plddr3_dacfifo [current_bd_instance .] axi_ad9371_dacfifo 128 128
ERROR: [BD 5-216] VLNV <analog.com:user:axi_dacfifo:1.0> is not supported for the current part.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing
"create_bd_cell -type ip -vlnv analog.com:user:axi_dacfifo:1.0 axi_dacfifo"
(procedure "p_plddr3_dacfifo" line 43)
invoked from within
"p_plddr3_dacfifo [current_bd_instance .] axi_ad9371_dacfifo 128 128"
(file "system_bd.tcl" line 5)

while executing
"source system_bd.tcl"
(procedure "adi_project_create" line 108)
invoked from within
"adi_project_create adrv9371x_zc706"
(file "./system_project.tcl" line 8)
update_compile_order -fileset sources_1

 

 

Regards

ARVIND

Outcomes