I want to use AD9161 and I am very low on FPGA and clock resources, so I want to know if my setup is possible.
My REF clock is 3840 MHz. I don't want to use internal PLL due to phase noise degradation.
I would like to generate a CW signal between 7 to 7.5GHz. Using mix mode. Is this possible with AD9161? I know that the interpolation in AD9161 is not bypassable. I wish to do this using the minimum FPGA resources needed, so the data rate should be the slowest possible with minimum lanes used.
The CW frequency changes every 100us.