Can the AD7124-4 be used for measurement of unipolar signal (0...1V) related to AVSS with GAIN = 2 without any external common-mode shifting ?
the common mode range must be between (AVSS − 0.05 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain). At a gain of 2, AVSS=0V, the min common mode voltage is 0.2V. So, for a 0 - 1V input, AIN- should be biased to 0.2V at least and AIN+ can swing from AIN- to (AIN- + 1V).
In unipolar mode, the ADC accepts only positive differential voltages ranges from +/-VREF/gain. In either case, the input voltage must be within the AVDD - 100mV and AVSS+100mV supply voltages in buffered mode. So if your signal does not exceed this common-mode voltage limits, you don't need one.
input voltage must be within the AVDD - 100mV and AVSS+100mV supply voltages in buffered mode
I agree that in buffered mode absolute voltage limit must be in the range that you've been specify, but GAIN = 2 is possible only with PGA enabled. And datasheet claims that with GAIN > 1 (PGA enabled) absolute voltage limit has to be in the range (AVSS - 0.05V .... AVDD + 0.05V)
So, my question was about "PGA enabled" mode and not about "buffered" mode. My signal (AVSS...AVSS+1.0V) is inside the range specified for PGA enabled mode (AVSS - 0.05V .... AVDD + 0.05V), but I would like to make sure that there is definitely no requirements for external common-mode shifting for such configuration. My question has been raised since I was noticed restrictions about common-mode input voltage in the datasheet:
These limitations are related to the common-mode rejection, but my signal is referenced to AVSS (AIN- equal to AVSS). Should I concern about these limitations in my case, when my signal will be referenced to AVSS without any additional external common-mode shifting ?
Sorry, I missed the Gain=2. The CMRR values are specified for the common mode voltage range mentioned in the footnote, but there is no specific restriction on the input common-mode voltage. The only restriction is that the absolute input voltages on each of the analog input pins should never exceed the (AVSS - 0.05V .... AVDD + 0.05V) when Gain >1.
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