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MIPI-CSI2 clock lane behaviour of ADV748x and ADV728x-M

Question asked by tomoto Employee on Oct 12, 2016
Latest reply on Oct 12, 2016 by JeyasudhaMuthuPerumal



According to datasheet description "MIPI VIDEO OUTPUT SPECIFICATIONS" of either products listed above,

the clock lane remains in high speed (HS) mode even when the data lane enters low power (LP) mode.


Does this mean either product support only continuous clock behaviour(stated as mandatory on CSI2 spec)?

*non-continuous clock behaviour stated as option


If yes, below MIPI-CSI2 CTS items are NOT applicable to ADV748x and ADV728x-M? 

Conformance Test Suite For D-PHY Physical Layer

2.4.13   Test 1.4.13 - Clock Lane HS Exit: TCLK-TRAIL Value

2.4.14   Test 1.4.14 - Clock Lane HS Exit: 30%-85% Post-EoT Rise Time(TREOT)

2.4.15   Test 1.4.15 - Clock Lane HS Exit: TEOT Value

2.4.16   Test 1.4.16 - Clock Lane HS Exit: THS-EXIT Value

2.2.3      Test 1.2.3 - Clock Lane LP-TX 15%-85% Rise Time (TRLP)