This is most likely not possible but is there a way to change the internal PLL settings for very low phase noise performance below -114dBc/Hz at 250KHz and -120dBc/Hz at 500KHz? Assume that lock time is not an issue at this point.
We don't recommend changing PLL parameters as it may unlock over temperature. ADI has provided a synt LUT for different reference frequencies which are verified and tested.
AD9361/4 SYNTHESIZER LOOK UP TABLE
Hi. I want to re-visit this question. I understand that ADI has a lot of pre-configured and tested functionality on AD9361. But I still would like to know if the internal PLL can be configured for a narrow loop bandwidth. Are there any guidelines, application notes, etc? ADI's discreet PLLs obviously support that functionality, and it's hard to believe that 9361's PLL architecture is very different. I'd appreciate any help. Thanks.
We don't recommend but still you want to configure it for lower loop band width refer below post
AD9361 RFPLL loop filter tuning
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