Analog Devices provides an AD9652 has Evaluation Kit called AD-FMCOMMS6-EBZ.
The user can plug it on a Xilinx ZC706 evaluation board in order test the ADC performances.
It supplies also Xilinx related reference design
The timing constrains of the ADC bus are missing for Git.
They are very important in order to prove the design feasibility in the FPGA.
Could you please provided them in order to enable the user to recompile your reference design?
The file are usually named .xdc.