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ADV7842 parallel mode

Question asked by dgomeziseebcn on Oct 11, 2016
Latest reply on Oct 20, 2016 by dgomeziseebcn



I'm checking UG-214.pdf document for the ADV7842 and I would like to know which is the output when I'm setting this:



- Parallel mode, 12 bit (OP_FORMAT_SEL[7:0]=0xC2)

- Channel: P23 - P12, auxiliary: Aux Yi,Cbi,Cri (OP_CH_SEL[7:5]=1, OP_CH_SEL[7:0]=0x20)




5.1.5 - Parallel Output Modes

The ADV7842 can provide three parallel output modes. These modes are selected via OP_FORMAT_SEL[7:0]. These parallel modes are available when processing a CVBS, an SVideo, or a component input up to 480i/576i input. There are two output pixel buses in these modes. The main bus can either be converted to a progressive format by using the I-to-P converter (refer to Section 7.18) or it can be in an interlaced format by bypassing the I-to-P converter. The auxiliary pixel bus will always be in an interlaced format.
In parallel mode, both the embedded synchronization and external synchronization are available to the main output block but only SAV/EAV is available to the auxiliary output block.
The auxiliary block has independent SAV/EAV controls to allow the output timing to be adjusted for this block. These controls are outlined in Section 7.22.7. Only one LLC clock output is available in parallel mode.

Which is the output? 12 bit 4:2:2 YCrCb?


In addition, this output is connected to a Linux system (v4l2) and I need to know this in order to configure it.