I am evaluating the HMC703 PLL IC for a product redesign and I encountered a few difficulties with the documentation (datasheet) and simulation using ADIsimPLL.
We need a PLL IC with frequency sweeping (ramping) capability in the 1-4 GHz range for a low power radar level sensing application.
Here are my questions:
- The HMC70x chips seem to be the only PLLs with sweeping capability, that at the same time feature a hardware "Trigger" pin to start the sweep. There would be other cheaper chips (such as the ADF4158) with the sweeping function, but none of the ADFxxxx parts (as far as I could see) seems to have a hardware trigger pin. Is this correct? How could the start of a sweep be controlled with an external logic signal on an ADF4158? (we need this function to *exactly* synchronize the sweep with the signal acquisition circuitry on the radar's receiver side).
- Throughout the HMC703 datasheet, there is a problem with greek letters. Many formulas are unreadable because of this:
Example 1 (on page 6-15):
Example 2 (on page 6-16):
Does anyone have access to an original hardcopy of the datasheet (or databook) and could he/she kindly share a scanned version thereof?
(in the mean time, I would suggest Analog Devices to check and fix the document...)
- (this question is related to the ADIsimPLL software):
I understand that ADIsimPLL software was designed with Analog Device's parts (ADFxxxx) in mind, not former Hittite (HMCxxx) products.
As such, it is a bit awkward to set up a frequency sweep with the HMC703. In fact, unlike in similar Analog Devices parts (e.g. ADF4158), the HMC703 does not have a register to set the NUMBER OF FREQUENCY STEPS. Instead, it has a register to set the STOP FREQUENCY.
As far as I understand, ADIsimPLL tries to mimick the HMC703 behavior while at the same time trying to preserve consistency among the various chips. As such, in the Data Panel, under Time Domain > Modulation, there is no STOP FREQUENCY field and the user must instead use the NUM STEPS field (after calculating the value to be entered there) to obtain the wanted result. That's OK, I got used to it...
But there's a bigger problem: the field Time Domain > Modulation > Ramp Dev > Step Size only allows 16 bit values (-32768 .... +32767). This may be correct for the ADF4158, but not for the HMC703 which has a 24 bit register for this purpose. Because of this limitation, I cannot simulate the desired frequency sweep. (I would need to enter a value of approximately 800000).
I assume that this is a bug and would kindly ask to have it fixed if that's the case. How long would it take to have a fixed version of ADIsimPLL?
- According to the HMC703's datasheet, this chip seems to have a far better figure of merit (noise floor) than any other similar ADFxxxx part operated in fractional mode. Is this difference *real* (and why?) or is it due to different test conditions that were applied on HMC (formerly Hittite) parts and ADF parts when measuring the noise performance?
I see similar differences when comparing - according to the datasheets - Analog Device's PLL chips with those from competitors (such as T.I.'s LMX2492). Are the competitor's chips *really* better in terms of noise as claimed by the datasheet?
And a final question: it seems that the ADIsimPLL software does not use the exact noise parameters specified in the datasheet for its PLL chips. Which of the two is now correct (datasheet or ADIsimPLL)?
Many thanks for your support!