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ZC706   AD-FMCOMMS3   A simple BBP for RF Transceivers

Question asked by qiyun on Oct 8, 2016
Latest reply on Oct 14, 2016 by qiyun

I am fairly new to the Zynq development process, and I am trying to implement a BBP on the hardware. I have been following this guide. A simple BBP for RF Transceivers [Analog Devices Wiki]  The guide is written for platform  ZC706+AD-FMCOMMS3. But I am trying to build it for ZED + AD-FMCOMMS4, as that's the hardware I have, so I have to build BOOT.BIN from scratch. I got all the source file from the website, and modified some ZC706 parameters to ZED.

 

 

I have cloned hdl repo, checked out hdl_2016_r1, built all relevant libraries. And I am using Vivado 2015.4.2.

 

The first problem I encountered:

(D:\DCP\rfbbp is my top level folder) When I am running D:\DCP\rfbbp\ip\axi_xcomm2ip\axi_xcomm2ip_ip.tcl, a IP designed given by the guide.When it is running it calls this file D:\DCP\rfbbp\hdl\library\scripts\adi_ip.tcl, and calls a function in it  

      proc adi_ip_properties {ip_name} {

         ........

         ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
         ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]

         ........

      }

There is a warning saying that the interface cannot be inferred. So I check the Xilix xml and change the two lines      ipx::infer_bus_interfaces xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
     ipx::infer_bus_interfaces xilinx.com:singal:reset_rtl:1.0 [ipx::current_core]

And the IP was successfully built. Is this the right way to solve the problem?

 

Second problem I encountered: 

The original file is D:\DCP\rfbbp\zc706\ZC706.tcl, but I changed all ZC706 to ZED, I changed the file path to D:\DCP\rfbbp\zed\zed.tcl, and this is the file content after change:

 

source D:/DCP/rfbbp/hdl/projects/scripts/adi_board.tcl
source D:/DCP/rfbbp/hdl/projects/scripts/adi_project.tcl

set sys_zynq 1

create_project zed . -part xc7z020clg484-1 -force

set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
set_property ip_repo_paths [list D:/DCP/rfbbp/hdl/library ../ip] [current_fileset]

update_ip_catalog

create_bd_design "system"
source D:/DCP/rfbbp/hdl/projects/common/zed/zed_system_bd.tcl
source D:/DCP/rfbbp/hdl/projects/fmcomms2/common/fmcomms2_bd.tcl

delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_i0]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_i0]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_q0]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_q0]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_i1]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_i1]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_q1]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_q1]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_dunf]]]

set axi_xcomm2ip [create_bd_cell -type ip -vlnv analog.com:user:axi_xcomm2ip:1.0 axi_xcomm2ip]
set_property -dict [list CONFIG.XCOMM2IP_1T1R_OR_2T2R_N {0}] $axi_xcomm2ip

ad_cpu_interconnect 0x79040000 axi_xcomm2ip

ad_connect axi_ad9361/clk axi_xcomm2ip/clk
ad_connect axi_ad9361/rst axi_xcomm2ip/rst
ad_connect axi_ad9361/adc_valid_i0 axi_xcomm2ip/adc_valid_i0
ad_connect axi_ad9361/adc_data_i0 axi_xcomm2ip/adc_data_i0
ad_connect axi_ad9361/adc_valid_q0 axi_xcomm2ip/adc_valid_q0
ad_connect axi_ad9361/adc_data_q0 axi_xcomm2ip/adc_data_q0
ad_connect axi_ad9361/adc_valid_i1 axi_xcomm2ip/adc_valid_i1
ad_connect axi_ad9361/adc_data_i1 axi_xcomm2ip/adc_data_i1
ad_connect axi_ad9361/adc_valid_q1 axi_xcomm2ip/adc_valid_q1
ad_connect axi_ad9361/adc_data_q1 axi_xcomm2ip/adc_data_q1
ad_connect axi_xcomm2ip/dac_valid_i0 axi_ad9361/dac_valid_i0
ad_connect axi_xcomm2ip/dac_data_i0 axi_ad9361/dac_data_i0
ad_connect axi_xcomm2ip/dac_valid_q0 axi_ad9361/dac_valid_q0
ad_connect axi_xcomm2ip/dac_data_q0 axi_ad9361/dac_data_q0
ad_connect axi_xcomm2ip/dac_valid_i1 axi_ad9361/dac_valid_i1
ad_connect axi_xcomm2ip/dac_data_i1 axi_ad9361/dac_data_i1
ad_connect axi_xcomm2ip/dac_valid_q1 axi_ad9361/dac_valid_q1
ad_connect axi_xcomm2ip/dac_data_q1 axi_ad9361/dac_data_q1
ad_connect axi_xcomm2ip/dac_dovf axi_ad9361/dac_dovf
ad_connect axi_xcomm2ip/dac_dunf axi_ad9361/dac_dunf

ad_connect util_ad9361_dac_upack/dac_data_0 axi_xcomm2ip/dma_data_i0
ad_connect util_ad9361_dac_upack/dac_data_1 axi_xcomm2ip/dma_data_q0
ad_connect util_ad9361_dac_upack/dac_data_2 axi_xcomm2ip/dma_data_i1
ad_connect util_ad9361_dac_upack/dac_data_3 axi_xcomm2ip/dma_data_q1
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_xcomm2ip/dma_dunf
ad_connect axi_xcomm2ip/dma_dovf GND

delete_bd_objs [get_bd_cells ila_adc]
delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]

regenerate_bd_layout
save_bd_design
validate_bd_design

generate_target {synthesis implementation} [get_files zed.srcs/sources_1/bd/system/system.bd]
make_wrapper -files [get_files zed.srcs/sources_1/bd/system/system.bd] -top
import_files -force -norecurse -fileset sources_1 zed.srcs/sources_1/bd/system/hdl/system_wrapper.v

adi_project_files zed [list \
"D:/DCP/rfbbp/hdl/library/common/ad_iobuf.v" \
"D:/DCP/rfbbp/hdl/projects/fmcomms2/zed/system_top.v" \
"D:/DCP/rfbbp/hdl/projects/fmcomms2/zed/system_constr.xdc"\
"D:/DCP/rfbbp/hdl/projects/common/zed/zed_system_constr.xdc" ]

adi_project_run zed

 

 

And this is the tcl message:

 

cd d:/DCP/rfbbp/zed
source ./zed.tcl
# source D:/DCP/rfbbp/hdl/projects/scripts/adi_board.tcl
## variable sys_cpu_interconnect_index
## variable sys_hp0_interconnect_index
## variable sys_hp1_interconnect_index
## variable sys_hp2_interconnect_index
## variable sys_hp3_interconnect_index
## variable sys_mem_interconnect_index
## set sys_cpu_interconnect_index 0
## set sys_hp0_interconnect_index -1
## set sys_hp1_interconnect_index -1
## set sys_hp2_interconnect_index -1
## set sys_hp3_interconnect_index -1
## set sys_mem_interconnect_index -1
## proc ad_connect_type {p_name} {
##
## set m_name ""
##
## if {$m_name eq ""} {set m_name [get_bd_intf_pins -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]}
##
## return $m_name
## }
## proc ad_connect {p_name_1 p_name_2} {
##
## if {($p_name_2 eq "GND") || ($p_name_2 eq "VCC")} {
## set p_size 1
## set p_msb [get_property left [get_bd_pins $p_name_1]]
## set p_lsb [get_property right [get_bd_pins $p_name_1]]
## if {($p_msb ne "") && ($p_lsb ne "")} {
## set p_size [expr (($p_msb + 1) - $p_lsb)]
## }
## set p_cell_name [regsub -all {/} $p_name_1 "_"]
## set p_cell_name "${p_cell_name}_${p_name_2}"
## if {$p_name_2 eq "VCC"} {
## set p_value -1
## } else {
## set p_value 0
## }
## puts "create_bd_cell(xlconstant) size($p_size) value($p_value) name($p_cell_name)"
## create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 $p_cell_name
## set_property CONFIG.CONST_WIDTH $p_size [get_bd_cells $p_cell_name]
## set_property CONFIG.CONST_VAL $p_value [get_bd_cells $p_cell_name]
## puts "connect_bd_net $p_cell_name/dout $p_name_1"
## connect_bd_net [get_bd_pins $p_cell_name/dout] [get_bd_pins $p_name_1]
## return
## }
##
## set m_name_1 [ad_connect_type $p_name_1]
## set m_name_2 [ad_connect_type $p_name_2]
##
## if {$m_name_1 eq ""} {
## if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
## puts "create_bd_intf_net $p_name_1"
## create_bd_intf_net $p_name_1
## }
## if {[get_property CLASS $m_name_2] eq "bd_pin"} {
## puts "create_bd_net $p_name_1"
## create_bd_net $p_name_1
## }
## set m_name_1 [ad_connect_type $p_name_1]
## }
##
## if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
## puts "connect_bd_intf_net $m_name_1 $m_name_2"
## connect_bd_intf_net $m_name_1 $m_name_2
## return
## }
##
## if {[get_property CLASS $m_name_1] eq "bd_pin"} {
## puts "connect_bd_net $m_name_1 $m_name_2"
## connect_bd_net $m_name_1 $m_name_2
## return
## }
##
## if {[get_property CLASS $m_name_1] eq "bd_net"} {
## puts "connect_bd_net -net $m_name_1 $m_name_2"
## connect_bd_net -net $m_name_1 $m_name_2
## return
## }
## }
## proc ad_mem_hp0_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
## if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
## }
## proc ad_mem_hp1_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
## if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
## }
## proc ad_mem_hp2_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
## if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
## }
## proc ad_mem_hp3_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
## if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
## }
## proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
##
## global sys_zynq
## global sys_ddr_addr_seg
## global sys_hp0_interconnect_index
## global sys_hp1_interconnect_index
## global sys_hp2_interconnect_index
## global sys_hp3_interconnect_index
## global sys_mem_interconnect_index
##
## set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
##
## if {$p_sel eq "MEM"} {
## if {$sys_mem_interconnect_index < 0} {
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect
## }
## set m_interconnect_index $sys_mem_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
## set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
## }
##
## if {$p_sel eq "HP0"} {
## if {$sys_hp0_interconnect_index < 0} {
## set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp0_interconnect
## }
## set m_interconnect_index $sys_hp0_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
## }
##
## if {$p_sel eq "HP1"} {
## if {$sys_hp1_interconnect_index < 0} {
## set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp1_interconnect
## }
## set m_interconnect_index $sys_hp1_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
## }
##
## if {$p_sel eq "HP2"} {
## if {$sys_hp2_interconnect_index < 0} {
## set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp2_interconnect
## }
## set m_interconnect_index $sys_hp2_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
## }
##
## if {$p_sel eq "HP3"} {
## if {$sys_hp3_interconnect_index < 0} {
## set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp3_interconnect
## }
## set m_interconnect_index $sys_hp3_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
## }
##
## set i_str "S$m_interconnect_index"
## if {$m_interconnect_index < 10} {
## set i_str "S0$m_interconnect_index"
## }
##
## set m_interconnect_index [expr $m_interconnect_index + 1]
##
## set p_intf_name [lrange [split $p_name "/"] end end]
## set p_cell_name [lrange [split $p_name "/"] 0 0]
## set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
## if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne "" ||
## $p_intf_clock eq $p_clk_source} {
## set p_intf_clock ""
## }
##
## if {$m_interconnect_index == 0} {
## set_property CONFIG.NUM_MI 1 $m_interconnect_cell
## set_property CONFIG.NUM_SI 1 $m_interconnect_cell
## ad_connect sys_cpu_resetn $m_interconnect_cell/ARESETN
## ad_connect $p_clk $m_interconnect_cell/ACLK
## ad_connect sys_cpu_resetn $m_interconnect_cell/M00_ARESETN
## ad_connect $p_clk $m_interconnect_cell/M00_ACLK
## ad_connect $m_interconnect_cell/M00_AXI $p_name
## if {$p_intf_clock ne ""} {
## ad_connect $p_clk $p_intf_clock
## }
## } else {
## set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
## ad_connect sys_cpu_resetn $m_interconnect_cell/${i_str}_ARESETN
## ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
## ad_connect $m_interconnect_cell/${i_str}_AXI $p_name
## if {$p_intf_clock ne ""} {
## ad_connect $p_clk $p_intf_clock
## }
## assign_bd_address $m_addr_seg
## }
##
## if {$m_interconnect_index == 3} {
## set_property CONFIG.STRATEGY {2} $m_interconnect_cell
## }
##
## if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
## }
## proc ad_cpu_interconnect {p_address p_name} {
##
## global sys_zynq
## global sys_cpu_interconnect_index
##
## set i_str "M$sys_cpu_interconnect_index"
## if {$sys_cpu_interconnect_index < 10} {
## set i_str "M0$sys_cpu_interconnect_index"
## }
##
## if {$sys_cpu_interconnect_index == 0} {
## create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect
## if {$sys_zynq == 1} {
## ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
## ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
## ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
## ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
## ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
## ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
## } else {
## ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
## ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
## ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
## ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
## ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
## }
## }
##
## if {$sys_zynq == 1} {
## set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
## } else {
## set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
## }
##
## set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
## set p_intf [get_bd_intf_pins -filter "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"\
## -of_objects [get_bd_cells $p_name]]
## set p_intf_name [lrange [split $p_intf "/"] end end]
## set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_name]]
## set p_intf_reset [get_bd_pins -filter "TYPE == rst && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_name]]
## if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
## set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
## if {$p_intf_reset ne ""} {
## set p_intf_reset [get_bd_pins $p_name/$p_intf_reset]
## }
## }
## if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
## set p_intf_clock ""
## }
## if {$p_intf_reset ne ""} {
## if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
## set p_intf_reset ""
## }
## }
##
## set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
##
## ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
## if {$p_intf_clock ne ""} {
## ad_connect sys_cpu_clk ${p_intf_clock}
## }
## ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
## if {$p_intf_reset ne ""} {
## ad_connect sys_cpu_resetn ${p_intf_reset}
## }
## ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
##
## set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
## set p_index 0
## foreach p_seg_name $p_seg {
## if {$p_index == 0} {
## set p_seg_range [get_property range $p_seg_name]
## create_bd_addr_seg -range $p_seg_range \
## -offset $p_address $sys_addr_cntrl_space \
## $p_seg_name "SEG_data_${p_name}"
## } else {
## assign_bd_address $p_seg_name
## }
## incr p_index
## }
## }
## proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
##
## global sys_zynq
##
## if {$sys_zynq == 1} {
## set p_index [regsub -all {[^0-9]} $p_ps_index ""]
## } else {
## set p_index [regsub -all {[^0-9]} $p_mb_index ""]
## }
##
## set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
## set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc/In$p_index]]
##
## puts "delete_bd_objs $p_net $p_pin"
## delete_bd_objs $p_net $p_pin
## ad_connect sys_concat_intc/In$p_index $p_name
## }
# source D:/DCP/rfbbp/hdl/projects/scripts/adi_project.tcl
## variable p_board
## variable p_device
## variable sys_zynq
## variable p_prcfg_init
## variable p_prcfg_list
## variable p_prcfg_status
## if {![info exists REQUIRED_VIVADO_VERSION]} {
## set REQUIRED_VIVADO_VERSION "2015.4.2"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## proc adi_project_create {project_name {mode 0}} {
##
## global ad_hdl_dir
## global ad_phdl_dir
## global p_board
## global p_device
## global sys_zynq
## global REQUIRED_VIVADO_VERSION
## global IGNORE_VERSION_CHECK
##
## set p_device "none"
## set p_board "none"
## set sys_zynq 0
##
## if [regexp "_ac701$" $project_name] {
## set p_device "xc7a200tfbg676-2"
## set p_board "xilinx.com:ac701:part0:1.0"
## set sys_zynq 0
## }
## if [regexp "_kc705$" $project_name] {
## set p_device "xc7k325tffg900-2"
## set p_board "xilinx.com:kc705:part0:1.1"
## set sys_zynq 0
## }
## if [regexp "_vc707$" $project_name] {
## set p_device "xc7vx485tffg1761-2"
## set p_board "xilinx.com:vc707:part0:1.1"
## set sys_zynq 0
## }
## if [regexp "_kcu105$" $project_name] {
## set p_device "xcku040-ffva1156-2-e"
## set p_board "xilinx.com:kcu105:part0:1.1"
## set sys_zynq 0
## }
## if [regexp "_zed$" $project_name] {
## set p_device "xc7z020clg484-1"
## set p_board "em.avnet.com:zed:part0:1.3"
## set sys_zynq 1
## }
## if [regexp "_zc702$" $project_name] {
## set p_device "xc7z020clg484-1"
## set p_board "xilinx.com:zc702:part0:1.2"
## set sys_zynq 1
## }
## if [regexp "_zc706$" $project_name] {
## set p_device "xc7z045ffg900-2"
## set p_board "xilinx.com:zc706:part0:1.2"
## set sys_zynq 1
## }
## if [regexp "_mitx045$" $project_name] {
## set p_device "xc7z045ffg900-2"
## set p_board "not-applicable"
## set sys_zynq 1
## }
## if [regexp "_pzsdr$" $project_name] {
## set p_device "xc7z035ifbg676-2L"
## set p_board "not-applicable"
## set sys_zynq 1
## }
##
## if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} {
## return -code error [format "ERROR: This project requires Vivado %s." $REQUIRED_VIVADO_VERSION]
## }
##
## if {$mode == 0} {
## set project_system_dir "./$project_name.srcs/sources_1/bd/system"
## create_project $project_name . -part $p_device -force
## } else {
## set project_system_dir ".srcs/sources_1/bd/system"
## create_project -in_memory -part $p_device
## }
##
## if {$mode == 1} {
## file mkdir $project_name.data
## }
##
## if {$p_board ne "not-applicable"} {
## set_property board_part $p_board [current_project]
## }
##
## set lib_dirs $ad_hdl_dir/library
## if {$ad_hdl_dir ne $ad_phdl_dir} {
## lappend lib_dirs $ad_phdl_dir/library
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
##
## set_msg_config -id {BD 41-1348} -new_severity info
## set_msg_config -id {BD 41-1343} -new_severity info
## set_msg_config -id {BD 41-1306} -new_severity info
## set_msg_config -id {IP_Flow 19-1687} -new_severity info
## set_msg_config -id {filemgmt 20-1763} -new_severity info
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity error
##
## create_bd_design "system"
## source system_bd.tcl
##
## regenerate_bd_layout
## save_bd_design
## validate_bd_design
##
## generate_target {synthesis implementation} [get_files $project_system_dir/system.bd]
## make_wrapper -files [get_files $project_system_dir/system.bd] -top
##
## if {$mode == 0} {
## import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
## } else {
## write_hwdef -file "$project_name.data/$project_name.hwdef"
## }
##
## if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
## add_files -norecurse -fileset sources_1 \
## "$ad_hdl_dir/projects/common/xilinx/compression_system_constr.xdc"
## }
##
## }
## proc adi_project_files {project_name project_files} {
##
## global ad_hdl_dir
## global ad_phdl_dir
##
## add_files -norecurse -fileset sources_1 $project_files
## set_property top system_top [current_fileset]
## }
## proc adi_project_run {project_name} {
##
## global ad_hdl_dir
## global ad_phdl_dir
## global p_board
##
## set project_system_dir "./$project_name.srcs/sources_1/bd/system"
##
## set_property constrs_type XDC [current_fileset -constrset]
##
## launch_runs synth_1
## wait_on_run synth_1
## open_run synth_1
## report_timing_summary -file timing_synth.log
##
## set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
## set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
## set_property STRATEGY "Performance_Explore" [get_runs impl_1]
##
## launch_runs impl_1 -to_step write_bitstream
## wait_on_run impl_1
## open_run impl_1
## report_timing_summary -file timing_impl.log
##
## file mkdir $project_name.sdk
## if [expr [get_property SLACK [get_timing_paths]] < 0] {
## file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_bad_timing.hdf
## } else {
## file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf
## }
##
##
## if [expr [get_property SLACK [get_timing_paths]] < 0] {
## return -code error [format "ERROR: Timing Constraints NOT met!"]
## }
## }
## proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
##
## global p_device
##
## set p_prefix "$project_name.data/$project_name"
##
## if {$prcfg_name eq ""} {
##
## read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
## read_verilog $hdl_files
## read_xdc $xdc_files
##
## synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
## write_checkpoint -force $p_prefix.synth.dcp
## close_project
##
## } else {
##
## create_project -in_memory -part $p_device
## read_verilog $hdl_files
## synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
## write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
## close_project
## }
## }
## proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
##
## global p_device
## global p_prcfg_init
## global p_prcfg_list
## global p_prcfg_status
##
## set p_prefix "$project_name.data/$project_name"
##
## if {$prcfg_name eq "default"} {
## set p_prcfg_status 0
## set p_prcfg_list ""
## set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
## file mkdir $project_name.sdk
## }
##
## if {$prcfg_name eq "default"} {
##
## open_checkpoint $p_prefix.synth.dcp -part $p_device
## read_xdc $xdc_files
## read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
## set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
## opt_design > $p_prefix.${prcfg_name}_opt.rds
## write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
## place_design > $p_prefix.${prcfg_name}_place.rds
## route_design > $p_prefix.${prcfg_name}_route.rds
##
## } else {
##
## open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
## lock_design -level routing
## read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
## read_xdc $xdc_files
## opt_design > $p_prefix.${prcfg_name}_opt.rds
## place_design > $p_prefix.${prcfg_name}_place.rds
## route_design > $p_prefix.${prcfg_name}_route.rds
## }
##
## write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
## report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
## report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
##
## if [expr [get_property SLACK [get_timing_paths]] < 0] {
## set p_prcfg_status 1
## puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
## }
##
## write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
## update_design -cell i_prcfg -black_box
## write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
## open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
## write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
## write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
## file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
##
## if {$prcfg_name ne "default"} {
## lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
## }
##
## if {$prcfg_name eq "default"} {
## file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
## }
## }
## proc adi_project_verify {project_name} {
##
## global p_prcfg_init
## global p_prcfg_list
## global p_prcfg_status
##
## set p_prefix "$project_name.data/$project_name"
##
## pr_verify -full_check -initial $p_prcfg_init \
## -additional $p_prcfg_list \
## -file $p_prefix.prcfg_verify.log
##
## if {$p_prcfg_status == 1} {
## return -code error [format "ERROR: Timing Constraints NOT met!"]
## }
## }
# set sys_zynq 1
# create_project zed . -part xc7z020clg484-1 -force
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'.
# set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
# set_property ip_repo_paths [list D:/DCP/rfbbp/hdl/library ../ip] [current_fileset]
# update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/DCP/rfbbp/hdl/library'.
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/DCP/rfbbp/ip'.
# create_bd_design "system"
Wrote : <d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/system.bd>
# source D:/DCP/rfbbp/hdl/projects/common/zed/zed_system_bd.tcl
## create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
## create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
## create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fmc
## create_bd_port -dir O spi0_csn_2_o
## create_bd_port -dir O spi0_csn_1_o
## create_bd_port -dir O spi0_csn_0_o
## create_bd_port -dir I spi0_csn_i
## create_bd_port -dir I spi0_clk_i
## create_bd_port -dir O spi0_clk_o
## create_bd_port -dir I spi0_sdo_i
## create_bd_port -dir O spi0_sdo_o
## create_bd_port -dir I spi0_sdi_i
## create_bd_port -dir O spi1_csn_2_o
## create_bd_port -dir O spi1_csn_1_o
## create_bd_port -dir O spi1_csn_0_o
## create_bd_port -dir I spi1_csn_i
## create_bd_port -dir I spi1_clk_i
## create_bd_port -dir O spi1_clk_o
## create_bd_port -dir I spi1_sdo_i
## create_bd_port -dir O spi1_sdo_o
## create_bd_port -dir I spi1_sdi_i
## create_bd_port -dir I -from 63 -to 0 gpio_i
## create_bd_port -dir O -from 63 -to 0 gpio_o
## create_bd_port -dir O -from 63 -to 0 gpio_t
## create_bd_port -dir O hdmi_out_clk
## create_bd_port -dir O hdmi_hsync
## create_bd_port -dir O hdmi_vsync
## create_bd_port -dir O hdmi_data_e
## create_bd_port -dir O -from 15 -to 0 hdmi_data
## create_bd_port -dir O -type clk i2s_mclk
## create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
## create_bd_port -dir I -from 1 -to 0 iic_mux_scl_i
## create_bd_port -dir O -from 1 -to 0 iic_mux_scl_o
## create_bd_port -dir O iic_mux_scl_t
## create_bd_port -dir I -from 1 -to 0 iic_mux_sda_i
## create_bd_port -dir O -from 1 -to 0 iic_mux_sda_o
## create_bd_port -dir O iic_mux_sda_t
## create_bd_port -dir I otg_vbusoc
## create_bd_port -dir O spdif
## create_bd_port -dir I -type intr ps_intr_00
## create_bd_port -dir I -type intr ps_intr_01
## create_bd_port -dir I -type intr ps_intr_02
## create_bd_port -dir I -type intr ps_intr_03
## create_bd_port -dir I -type intr ps_intr_04
## create_bd_port -dir I -type intr ps_intr_05
## create_bd_port -dir I -type intr ps_intr_06
## create_bd_port -dir I -type intr ps_intr_07
## create_bd_port -dir I -type intr ps_intr_08
## create_bd_port -dir I -type intr ps_intr_09
## create_bd_port -dir I -type intr ps_intr_10
## create_bd_port -dir I -type intr ps_intr_12
## create_bd_port -dir I -type intr ps_intr_13
## set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
## set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZedBoard}] $sys_ps7
INFO: [PS7-1] Applying Board Preset ZedBoard...
## set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
## set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
## set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
## set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
## set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
## set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
## set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
## set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
## set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
## set_property -dict [list CONFIG.USE_BOARD_FLOW {true} ] $axi_iic_main
## set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
## set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]
## set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
## set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
## set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
## set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
## set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
## set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
## set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
## set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
## set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
## set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
## set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
## set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
## set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
## set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
## set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
## set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
## set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
## set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
## set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
## set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
## set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
## set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
## set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
## set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
## set axi_iic_fmc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_fmc]
## ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
create_bd_net sys_cpu_clk
connect_bd_net -net /sys_cpu_clk /sys_ps7/FCLK_CLK0
## ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
create_bd_net sys_200m_clk
connect_bd_net -net /sys_200m_clk /sys_ps7/FCLK_CLK1
## ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
create_bd_net sys_cpu_reset
connect_bd_net -net /sys_cpu_reset /sys_rstgen/peripheral_reset
## ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
create_bd_net sys_cpu_resetn
connect_bd_net -net /sys_cpu_resetn /sys_rstgen/peripheral_aresetn
## ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
connect_bd_net -net /sys_cpu_clk /sys_rstgen/slowest_sync_clk
## ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
connect_bd_net /sys_rstgen/ext_reset_in /sys_ps7/FCLK_RESET0_N
## ad_connect ddr sys_ps7/DDR
connect_bd_intf_net /ddr /sys_ps7/DDR
## ad_connect gpio_i sys_ps7/GPIO_I
connect_bd_net /gpio_i /sys_ps7/GPIO_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_I is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
## ad_connect gpio_o sys_ps7/GPIO_O
connect_bd_net /gpio_o /sys_ps7/GPIO_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
## ad_connect gpio_t sys_ps7/GPIO_T
connect_bd_net /gpio_t /sys_ps7/GPIO_T
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/GPIO_T is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
## ad_connect fixed_io sys_ps7/FIXED_IO
connect_bd_intf_net /fixed_io /sys_ps7/FIXED_IO
## ad_connect iic_fmc axi_iic_fmc/iic
connect_bd_intf_net /iic_fmc /axi_iic_fmc/IIC
## ad_connect sys_200m_clk axi_hdmi_clkgen/clk
connect_bd_net -net /sys_200m_clk /axi_hdmi_clkgen/clk
## ad_connect axi_iic_main/IIC sys_i2c_mixer/upstream
connect_bd_intf_net /axi_iic_main/IIC /sys_i2c_mixer/upstream
## ad_connect iic_mux_scl_i sys_i2c_mixer/downstream_scl_i
connect_bd_net /iic_mux_scl_i /sys_i2c_mixer/downstream_scl_I
## ad_connect iic_mux_scl_o sys_i2c_mixer/downstream_scl_o
connect_bd_net /iic_mux_scl_o /sys_i2c_mixer/downstream_scl_O
## ad_connect iic_mux_scl_t sys_i2c_mixer/downstream_scl_t
connect_bd_net /iic_mux_scl_t /sys_i2c_mixer/downstream_scl_T
## ad_connect iic_mux_sda_i sys_i2c_mixer/downstream_sda_i
connect_bd_net /iic_mux_sda_i /sys_i2c_mixer/downstream_sda_I
## ad_connect iic_mux_sda_o sys_i2c_mixer/downstream_sda_o
connect_bd_net /iic_mux_sda_o /sys_i2c_mixer/downstream_sda_O
## ad_connect iic_mux_sda_t sys_i2c_mixer/downstream_sda_t
connect_bd_net /iic_mux_sda_t /sys_i2c_mixer/downstream_sda_T
## ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
connect_bd_net /sys_logic_inv/Res /sys_ps7/USB0_VBUS_PWRFAULT
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/USB0_VBUS_PWRFAULT is being overridden by the user. This pin will not be connected as a part of interface connection USBIND_0
## ad_connect otg_vbusoc sys_logic_inv/Op1
connect_bd_net /otg_vbusoc /sys_logic_inv/Op1
## ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
connect_bd_net /spi0_csn_2_o /sys_ps7/SPI0_SS2_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
connect_bd_net /spi0_csn_1_o /sys_ps7/SPI0_SS1_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
connect_bd_net /spi0_csn_0_o /sys_ps7/SPI0_SS_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
connect_bd_net /spi0_csn_i /sys_ps7/SPI0_SS_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
connect_bd_net /spi0_clk_i /sys_ps7/SPI0_SCLK_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
connect_bd_net /spi0_clk_o /sys_ps7/SPI0_SCLK_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
connect_bd_net /spi0_sdo_i /sys_ps7/SPI0_MOSI_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
connect_bd_net /spi0_sdo_o /sys_ps7/SPI0_MOSI_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
connect_bd_net /spi0_sdi_i /sys_ps7/SPI0_MISO_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI0_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_0
## ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
connect_bd_net /spi1_csn_2_o /sys_ps7/SPI1_SS2_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS2_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
connect_bd_net /spi1_csn_1_o /sys_ps7/SPI1_SS1_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS1_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
connect_bd_net /spi1_csn_0_o /sys_ps7/SPI1_SS_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
connect_bd_net /spi1_csn_i /sys_ps7/SPI1_SS_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SS_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
connect_bd_net /spi1_clk_i /sys_ps7/SPI1_SCLK_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
connect_bd_net /spi1_clk_o /sys_ps7/SPI1_SCLK_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_SCLK_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
connect_bd_net /spi1_sdo_i /sys_ps7/SPI1_MOSI_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
connect_bd_net /spi1_sdo_o /sys_ps7/SPI1_MOSI_O
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MOSI_O is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
connect_bd_net /spi1_sdi_i /sys_ps7/SPI1_MISO_I
WARNING: [BD 41-1306] The connection to interface pin /sys_ps7/SPI1_MISO_I is being overridden by the user. This pin will not be connected as a part of interface connection SPI_1
## ad_connect sys_cpu_clk axi_hdmi_core/vdma_clk
connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/vdma_clk
## ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_axis_mm2s_aclk
## ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
connect_bd_net /axi_hdmi_core/hdmi_clk /axi_hdmi_clkgen/clk_0
## ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
connect_bd_net /axi_hdmi_core/hdmi_out_clk /hdmi_out_clk
## ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
connect_bd_net /axi_hdmi_core/hdmi_16_hsync /hdmi_hsync
## ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync
connect_bd_net /axi_hdmi_core/hdmi_16_vsync /hdmi_vsync
## ad_connect axi_hdmi_core/hdmi_16_data_e hdmi_data_e
connect_bd_net /axi_hdmi_core/hdmi_16_data_e /hdmi_data_e
## ad_connect axi_hdmi_core/hdmi_16_data hdmi_data
connect_bd_net /axi_hdmi_core/hdmi_16_data /hdmi_data
## ad_connect axi_hdmi_core/vdma_valid axi_hdmi_dma/m_axis_mm2s_tvalid
connect_bd_net /axi_hdmi_core/vdma_valid /axi_hdmi_dma/m_axis_mm2s_tvalid
WARNING: [BD 41-1306] The connection to interface pin /axi_hdmi_dma/m_axis_mm2s_tvalid is being overridden by the user. This pin will not be connected as a part of interface connection M_AXIS_MM2S
## ad_connect axi_hdmi_core/vdma_data axi_hdmi_dma/m_axis_mm2s_tdata
connect_bd_net /axi_hdmi_core/vdma_data /axi_hdmi_dma/m_axis_mm2s_tdata
WARNING: [BD 41-1306] The connection to interface pin /axi_hdmi_dma/m_axis_mm2s_tdata is being overridden by the user. This pin will not be connected as a part of interface connection M_AXIS_MM2S
## ad_connect axi_hdmi_core/vdma_ready axi_hdmi_dma/m_axis_mm2s_tready
connect_bd_net /axi_hdmi_core/vdma_ready /axi_hdmi_dma/m_axis_mm2s_tready
WARNING: [BD 41-1306] The connection to interface pin /axi_hdmi_dma/m_axis_mm2s_tready is being overridden by the user. This pin will not be connected as a part of interface connection M_AXIS_MM2S
## ad_connect axi_hdmi_core/vdma_fs axi_hdmi_dma/mm2s_fsync
connect_bd_net /axi_hdmi_core/vdma_fs /axi_hdmi_dma/mm2s_fsync
## ad_connect axi_hdmi_core/vdma_fs axi_hdmi_core/vdma_fs_ret
connect_bd_net /axi_hdmi_core/vdma_fs /axi_hdmi_core/vdma_fs_ret
## ad_connect sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/DMA_REQ_ACLK
## ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA0_ACLK
## ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
connect_bd_intf_net /sys_ps7/DMA0_REQ /axi_spdif_tx_core/DMA_REQ
## ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
connect_bd_intf_net /sys_ps7/DMA0_ACK /axi_spdif_tx_core/DMA_ACK
## ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/DMA_REQ_RSTN
## ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
connect_bd_net -net /sys_200m_clk /sys_audio_clkgen/clk_in1
## ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
connect_bd_net -net /sys_cpu_resetn /sys_audio_clkgen/resetn
## ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
connect_bd_net /sys_audio_clkgen/clk_out1 /axi_spdif_tx_core/spdif_data_clk
## ad_connect spdif axi_spdif_tx_core/spdif_tx_o
connect_bd_net /spdif /axi_spdif_tx_core/spdif_tx_o
## ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/DMA_REQ_RX_ACLK
## ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/DMA_REQ_TX_ACLK
## ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK
connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA1_ACLK
## ad_connect sys_cpu_clk sys_ps7/DMA2_ACLK
connect_bd_net -net /sys_cpu_clk /sys_ps7/DMA2_ACLK
## ad_connect sys_audio_clkgen/clk_out1 i2s_mclk
connect_bd_net /sys_audio_clkgen/clk_out1 /i2s_mclk
## ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
connect_bd_net /sys_audio_clkgen/clk_out1 /axi_i2s_adi/DATA_CLK_I
## ad_connect i2s axi_i2s_adi/I2S
connect_bd_intf_net /i2s /axi_i2s_adi/I2S
## ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
connect_bd_intf_net /sys_ps7/DMA1_REQ /axi_i2s_adi/DMA_REQ_TX
## ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
connect_bd_intf_net /sys_ps7/DMA1_ACK /axi_i2s_adi/DMA_ACK_TX
## ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/DMA_REQ_TX_RSTN
## ad_connect sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
connect_bd_intf_net /sys_ps7/DMA2_REQ /axi_i2s_adi/DMA_REQ_RX
## ad_connect sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
connect_bd_intf_net /sys_ps7/DMA2_ACK /axi_i2s_adi/DMA_ACK_RX
## ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/DMA_REQ_RX_RSTN
## ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
connect_bd_net /sys_concat_intc/dout /sys_ps7/IRQ_F2P
## ad_connect sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
connect_bd_net /sys_concat_intc/In15 /axi_hdmi_dma/mm2s_introut
## ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
connect_bd_net /sys_concat_intc/In14 /axi_iic_main/iic2intc_irpt
## ad_connect sys_concat_intc/In13 ps_intr_13
connect_bd_net /sys_concat_intc/In13 /ps_intr_13
## ad_connect sys_concat_intc/In12 ps_intr_12
connect_bd_net /sys_concat_intc/In12 /ps_intr_12
## ad_connect sys_concat_intc/In11 axi_iic_fmc/iic2intc_irpt
connect_bd_net /sys_concat_intc/In11 /axi_iic_fmc/iic2intc_irpt
## ad_connect sys_concat_intc/In10 ps_intr_10
connect_bd_net /sys_concat_intc/In10 /ps_intr_10
## ad_connect sys_concat_intc/In9 ps_intr_09
connect_bd_net /sys_concat_intc/In9 /ps_intr_09
## ad_connect sys_concat_intc/In8 ps_intr_08
connect_bd_net /sys_concat_intc/In8 /ps_intr_08
## ad_connect sys_concat_intc/In7 ps_intr_07
connect_bd_net /sys_concat_intc/In7 /ps_intr_07
## ad_connect sys_concat_intc/In6 ps_intr_06
connect_bd_net /sys_concat_intc/In6 /ps_intr_06
## ad_connect sys_concat_intc/In5 ps_intr_05
connect_bd_net /sys_concat_intc/In5 /ps_intr_05
## ad_connect sys_concat_intc/In4 ps_intr_04
connect_bd_net /sys_concat_intc/In4 /ps_intr_04
## ad_connect sys_concat_intc/In3 ps_intr_03
connect_bd_net /sys_concat_intc/In3 /ps_intr_03
## ad_connect sys_concat_intc/In2 ps_intr_02
connect_bd_net /sys_concat_intc/In2 /ps_intr_02
## ad_connect sys_concat_intc/In1 ps_intr_01
connect_bd_net /sys_concat_intc/In1 /ps_intr_01
## ad_connect sys_concat_intc/In0 ps_intr_00
connect_bd_net /sys_concat_intc/In0 /ps_intr_00
## ad_cpu_interconnect 0x41600000 axi_iic_main
connect_bd_net -net /sys_cpu_clk /sys_ps7/M_AXI_GP0_ACLK
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/ACLK
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/S00_ACLK
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/S00_ARESETN
connect_bd_intf_net /axi_cpu_interconnect/S00_AXI /sys_ps7/M_AXI_GP0
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M00_ACLK
connect_bd_net -net /sys_cpu_clk /axi_iic_main/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M00_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_iic_main/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M00_AXI /axi_iic_main/S_AXI
## ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M01_ACLK
connect_bd_net -net /sys_cpu_clk /axi_hdmi_clkgen/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M01_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_hdmi_clkgen/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M01_AXI /axi_hdmi_clkgen/s_axi
## ad_cpu_interconnect 0x43000000 axi_hdmi_dma
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M02_ACLK
connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/s_axi_lite_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M02_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_hdmi_dma/axi_resetn
connect_bd_intf_net /axi_cpu_interconnect/M02_AXI /axi_hdmi_dma/S_AXI_LITE
## ad_cpu_interconnect 0x70e00000 axi_hdmi_core
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M03_ACLK
connect_bd_net -net /sys_cpu_clk /axi_hdmi_core/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M03_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_hdmi_core/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M03_AXI /axi_hdmi_core/s_axi
## ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M04_ACLK
connect_bd_net -net /sys_cpu_clk /axi_spdif_tx_core/S_AXI_ACLK
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M04_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_spdif_tx_core/S_AXI_ARESETN
connect_bd_intf_net /axi_cpu_interconnect/M04_AXI /axi_spdif_tx_core/s_axi
## ad_cpu_interconnect 0x77600000 axi_i2s_adi
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M05_ACLK
connect_bd_net -net /sys_cpu_clk /axi_i2s_adi/S_AXI_ACLK
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M05_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_i2s_adi/S_AXI_ARESETN
connect_bd_intf_net /axi_cpu_interconnect/M05_AXI /axi_i2s_adi/s_axi
## ad_cpu_interconnect 0x41620000 axi_iic_fmc
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M06_ACLK
connect_bd_net -net /sys_cpu_clk /axi_iic_fmc/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M06_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_iic_fmc/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M06_AXI /axi_iic_fmc/S_AXI
## ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
connect_bd_net -net /sys_cpu_resetn /axi_hp0_interconnect/ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp0_interconnect/ACLK
connect_bd_net -net /sys_cpu_resetn /axi_hp0_interconnect/M00_ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp0_interconnect/M00_ACLK
connect_bd_intf_net /axi_hp0_interconnect/M00_AXI /sys_ps7/S_AXI_HP0
connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP0_ACLK
## ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
connect_bd_net -net /sys_cpu_resetn /axi_hp0_interconnect/S00_ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp0_interconnect/S00_ACLK
connect_bd_intf_net /axi_hp0_interconnect/S00_AXI /axi_hdmi_dma/M_AXI_MM2S
connect_bd_net -net /sys_cpu_clk /axi_hdmi_dma/m_axi_mm2s_aclk
</sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM> is being mapped into </axi_hdmi_dma/Data_MM2S> at <0x00000000 [ 512M ]>
# source D:/DCP/rfbbp/hdl/projects/fmcomms2/common/fmcomms2_bd.tcl
## create_bd_port -dir I rx_clk_in_p
## create_bd_port -dir I rx_clk_in_n
## create_bd_port -dir I rx_frame_in_p
## create_bd_port -dir I rx_frame_in_n
## create_bd_port -dir I -from 5 -to 0 rx_data_in_p
## create_bd_port -dir I -from 5 -to 0 rx_data_in_n
## create_bd_port -dir O tx_clk_out_p
## create_bd_port -dir O tx_clk_out_n
## create_bd_port -dir O tx_frame_out_p
## create_bd_port -dir O tx_frame_out_n
## create_bd_port -dir O -from 5 -to 0 tx_data_out_p
## create_bd_port -dir O -from 5 -to 0 tx_data_out_n
## create_bd_port -dir O enable
## create_bd_port -dir O txnrx
## create_bd_port -dir I up_enable
## create_bd_port -dir I up_txnrx
## create_bd_port -dir O tdd_sync_o
## create_bd_port -dir I tdd_sync_i
## create_bd_port -dir O tdd_sync_t
## set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
## set_property -dict [list CONFIG.ID {0}] $axi_ad9361
## set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
## set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
## set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
## set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
## set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'SYNC_TRANSFER_START' of cell '/axi_ad9361_dac_dma' is ignored
## set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
## set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
## set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
## set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
## set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
## set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_dac_upack
## set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack
## set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
## set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
## set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
## set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
## set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
## set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
## set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
## set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
## set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma
## set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
## set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_pack
## set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack
## set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo]
## set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo
## set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo
## set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
## set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
## set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
## ad_connect sys_200m_clk axi_ad9361/delay_clk
connect_bd_net -net /sys_200m_clk /axi_ad9361/delay_clk
## ad_connect axi_ad9361_clk axi_ad9361/l_clk
create_bd_net axi_ad9361_clk
connect_bd_net -net /axi_ad9361_clk /axi_ad9361/l_clk
## ad_connect axi_ad9361_clk axi_ad9361/clk
connect_bd_net -net /axi_ad9361_clk /axi_ad9361/clk
## ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
connect_bd_net /rx_clk_in_p /axi_ad9361/rx_clk_in_p
## ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
connect_bd_net /rx_clk_in_n /axi_ad9361/rx_clk_in_n
## ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
connect_bd_net /rx_frame_in_p /axi_ad9361/rx_frame_in_p
## ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
connect_bd_net /rx_frame_in_n /axi_ad9361/rx_frame_in_n
## ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
connect_bd_net /rx_data_in_p /axi_ad9361/rx_data_in_p
## ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
connect_bd_net /rx_data_in_n /axi_ad9361/rx_data_in_n
## ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
connect_bd_net /tx_clk_out_p /axi_ad9361/tx_clk_out_p
## ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
connect_bd_net /tx_clk_out_n /axi_ad9361/tx_clk_out_n
## ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
connect_bd_net /tx_frame_out_p /axi_ad9361/tx_frame_out_p
## ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
connect_bd_net /tx_frame_out_n /axi_ad9361/tx_frame_out_n
## ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
connect_bd_net /tx_data_out_p /axi_ad9361/tx_data_out_p
## ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
connect_bd_net /tx_data_out_n /axi_ad9361/tx_data_out_n
## ad_connect enable axi_ad9361/enable
connect_bd_net /enable /axi_ad9361/enable
## ad_connect txnrx axi_ad9361/txnrx
connect_bd_net /txnrx /axi_ad9361/txnrx
## ad_connect up_enable axi_ad9361/up_enable
connect_bd_net /up_enable /axi_ad9361/up_enable
## ad_connect up_txnrx axi_ad9361/up_txnrx
connect_bd_net /up_txnrx /axi_ad9361/up_txnrx
## ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
connect_bd_net -net /axi_ad9361_clk /util_ad9361_adc_fifo/din_clk
## ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
connect_bd_net /axi_ad9361/rst /util_ad9361_adc_fifo/din_rst
## ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk
connect_bd_net -net /sys_cpu_clk /util_ad9361_adc_fifo/dout_clk
## ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
connect_bd_net -net /sys_cpu_resetn /util_ad9361_adc_fifo/dout_rstn
## ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk
connect_bd_net -net /sys_cpu_clk /util_ad9361_adc_pack/adc_clk
## ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst
connect_bd_net -net /sys_cpu_reset /util_ad9361_adc_pack/adc_rst
## ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/fifo_wr_clk
## ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
connect_bd_net /axi_ad9361/adc_enable_i0 /util_ad9361_adc_fifo/din_enable_0
## ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
connect_bd_net /axi_ad9361/adc_valid_i0 /util_ad9361_adc_fifo/din_valid_0
## ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
connect_bd_net /axi_ad9361/adc_data_i0 /util_ad9361_adc_fifo/din_data_0
## ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
connect_bd_net /axi_ad9361/adc_enable_q0 /util_ad9361_adc_fifo/din_enable_1
## ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
connect_bd_net /axi_ad9361/adc_valid_q0 /util_ad9361_adc_fifo/din_valid_1
## ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
connect_bd_net /axi_ad9361/adc_data_q0 /util_ad9361_adc_fifo/din_data_1
## ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
connect_bd_net /axi_ad9361/adc_enable_i1 /util_ad9361_adc_fifo/din_enable_2
## ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
connect_bd_net /axi_ad9361/adc_valid_i1 /util_ad9361_adc_fifo/din_valid_2
## ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
connect_bd_net /axi_ad9361/adc_data_i1 /util_ad9361_adc_fifo/din_data_2
## ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
connect_bd_net /axi_ad9361/adc_enable_q1 /util_ad9361_adc_fifo/din_enable_3
## ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
connect_bd_net /axi_ad9361/adc_valid_q1 /util_ad9361_adc_fifo/din_valid_3
## ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
connect_bd_net /axi_ad9361/adc_data_q1 /util_ad9361_adc_fifo/din_data_3
## ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
connect_bd_net /util_ad9361_adc_fifo/dout_enable_0 /util_ad9361_adc_pack/adc_enable_0
## ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
connect_bd_net /util_ad9361_adc_fifo/dout_valid_0 /util_ad9361_adc_pack/adc_valid_0
## ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
connect_bd_net /util_ad9361_adc_fifo/dout_data_0 /util_ad9361_adc_pack/adc_data_0
## ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
connect_bd_net /util_ad9361_adc_fifo/dout_enable_1 /util_ad9361_adc_pack/adc_enable_1
## ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
connect_bd_net /util_ad9361_adc_fifo/dout_valid_1 /util_ad9361_adc_pack/adc_valid_1
## ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
connect_bd_net /util_ad9361_adc_fifo/dout_data_1 /util_ad9361_adc_pack/adc_data_1
## ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
connect_bd_net /util_ad9361_adc_fifo/dout_enable_2 /util_ad9361_adc_pack/adc_enable_2
## ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
connect_bd_net /util_ad9361_adc_fifo/dout_valid_2 /util_ad9361_adc_pack/adc_valid_2
## ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
connect_bd_net /util_ad9361_adc_fifo/dout_data_2 /util_ad9361_adc_pack/adc_data_2
## ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
connect_bd_net /util_ad9361_adc_fifo/dout_enable_3 /util_ad9361_adc_pack/adc_enable_3
## ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
connect_bd_net /util_ad9361_adc_fifo/dout_valid_3 /util_ad9361_adc_pack/adc_valid_3
## ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
connect_bd_net /util_ad9361_adc_fifo/dout_data_3 /util_ad9361_adc_pack/adc_data_3
## ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
connect_bd_net /util_ad9361_adc_pack/adc_valid /axi_ad9361_adc_dma/fifo_wr_en
WARNING: [BD 41-1306] The connection to interface pin /axi_ad9361_adc_dma/fifo_wr_en is being overridden by the user. This pin will not be connected as a part of interface connection fifo_wr
## ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
connect_bd_net /util_ad9361_adc_pack/adc_sync /axi_ad9361_adc_dma/fifo_wr_sync
WARNING: [BD 41-1306] The connection to interface pin /axi_ad9361_adc_dma/fifo_wr_sync is being overridden by the user. This pin will not be connected as a part of interface connection fifo_wr
## ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
connect_bd_net /util_ad9361_adc_pack/adc_data /axi_ad9361_adc_dma/fifo_wr_din
WARNING: [BD 41-1306] The connection to interface pin /axi_ad9361_adc_dma/fifo_wr_din is being overridden by the user. This pin will not be connected as a part of interface connection fifo_wr
## ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
connect_bd_net /axi_ad9361_adc_dma/fifo_wr_overflow /util_ad9361_adc_fifo/dout_ovf
WARNING: [BD 41-1306] The connection to interface pin /axi_ad9361_adc_dma/fifo_wr_overflow is being overridden by the user. This pin will not be connected as a part of interface connection fifo_wr
## ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
connect_bd_net /util_ad9361_adc_fifo/din_ovf /axi_ad9361/adc_dovf
## ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk
connect_bd_net -net /axi_ad9361_clk /util_ad9361_dac_upack/dac_clk
## ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
connect_bd_net -net /axi_ad9361_clk /axi_ad9361_dac_dma/fifo_rd_clk
## ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
connect_bd_net /util_ad9361_dac_upack/dac_enable_0 /axi_ad9361/dac_enable_i0
## ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
connect_bd_net /util_ad9361_dac_upack/dac_valid_0 /axi_ad9361/dac_valid_i0
## ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
connect_bd_net /util_ad9361_dac_upack/dac_data_0 /axi_ad9361/dac_data_i0
## ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
connect_bd_net /util_ad9361_dac_upack/dac_enable_1 /axi_ad9361/dac_enable_q0
## ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
connect_bd_net /util_ad9361_dac_upack/dac_valid_1 /axi_ad9361/dac_valid_q0
## ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
connect_bd_net /util_ad9361_dac_upack/dac_data_1 /axi_ad9361/dac_data_q0
## ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
connect_bd_net /util_ad9361_dac_upack/dac_enable_2 /axi_ad9361/dac_enable_i1
## ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
connect_bd_net /util_ad9361_dac_upack/dac_valid_2 /axi_ad9361/dac_valid_i1
## ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
connect_bd_net /util_ad9361_dac_upack/dac_data_2 /axi_ad9361/dac_data_i1
## ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
connect_bd_net /util_ad9361_dac_upack/dac_enable_3 /axi_ad9361/dac_enable_q1
## ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
connect_bd_net /util_ad9361_dac_upack/dac_valid_3 /axi_ad9361/dac_valid_q1
## ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
connect_bd_net /util_ad9361_dac_upack/dac_data_3 /axi_ad9361/dac_data_q1
## ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
connect_bd_net /util_ad9361_dac_upack/dac_valid /axi_ad9361_dac_dma/fifo_rd_en
WARNING: [BD 41-1306] The connection to interface pin /axi_ad9361_dac_dma/fifo_rd_en is being overridden by the user. This pin will not be connected as a part of interface connection fifo_rd
## ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
connect_bd_net /util_ad9361_dac_upack/dac_data /axi_ad9361_dac_dma/fifo_rd_dout
WARNING: [BD 41-1306] The connection to interface pin /axi_ad9361_dac_dma/fifo_rd_dout is being overridden by the user. This pin will not be connected as a part of interface connection fifo_rd
## ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
connect_bd_net /axi_ad9361_dac_dma/fifo_rd_underflow /axi_ad9361/dac_dunf
WARNING: [BD 41-1306] The connection to interface pin /axi_ad9361_dac_dma/fifo_rd_underflow is being overridden by the user. This pin will not be connected as a part of interface connection fifo_rd
## ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
connect_bd_net -net /sys_cpu_clk /util_ad9361_tdd_sync/clk
## ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
connect_bd_net -net /sys_cpu_resetn /util_ad9361_tdd_sync/rstn
## ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
connect_bd_net /util_ad9361_tdd_sync/sync_out /axi_ad9361/tdd_sync
## ad_connect util_ad9361_tdd_sync/sync_en axi_ad9361/tdd_sync_en
connect_bd_net /util_ad9361_tdd_sync/sync_en /axi_ad9361/tdd_sync_en
WARNING: [BD 41-1306] The connection to interface pin /util_ad9361_tdd_sync/sync_en is being overridden by the user. This pin will not be connected as a part of interface connection sync
## ad_connect util_ad9361_tdd_sync/sync_type axi_ad9361/tdd_terminal_type
connect_bd_net /util_ad9361_tdd_sync/sync_type /axi_ad9361/tdd_terminal_type
## ad_connect tdd_sync_t axi_ad9361/tdd_terminal_type
connect_bd_net /tdd_sync_t /axi_ad9361/tdd_terminal_type
## ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
connect_bd_net /tdd_sync_o /util_ad9361_tdd_sync/sync_out
## ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in
connect_bd_net /tdd_sync_i /util_ad9361_tdd_sync/sync_in
## ad_cpu_interconnect 0x79020000 axi_ad9361
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M07_ACLK
connect_bd_net -net /sys_cpu_clk /axi_ad9361/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M07_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_ad9361/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M07_AXI /axi_ad9361/s_axi
## ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M08_ACLK
connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M08_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M08_AXI /axi_ad9361_adc_dma/s_axi
## ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M09_ACLK
connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M09_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M09_AXI /axi_ad9361_dac_dma/s_axi
## ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
connect_bd_net -net /sys_cpu_resetn /axi_hp1_interconnect/ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp1_interconnect/ACLK
connect_bd_net -net /sys_cpu_resetn /axi_hp1_interconnect/M00_ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp1_interconnect/M00_ACLK
connect_bd_intf_net /axi_hp1_interconnect/M00_AXI /sys_ps7/S_AXI_HP1
connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP1_ACLK
## ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
connect_bd_net -net /sys_cpu_resetn /axi_hp1_interconnect/S00_ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp1_interconnect/S00_ACLK
connect_bd_intf_net /axi_hp1_interconnect/S00_AXI /axi_ad9361_adc_dma/m_dest_axi
connect_bd_net -net /sys_cpu_clk /axi_ad9361_adc_dma/m_dest_axi_aclk
</sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is being mapped into </axi_ad9361_adc_dma/m_dest_axi> at <0x00000000 [ 512M ]>
## ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
connect_bd_net -net /sys_cpu_resetn /axi_hp2_interconnect/ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp2_interconnect/ACLK
connect_bd_net -net /sys_cpu_resetn /axi_hp2_interconnect/M00_ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp2_interconnect/M00_ACLK
connect_bd_intf_net /axi_hp2_interconnect/M00_AXI /sys_ps7/S_AXI_HP2
connect_bd_net -net /sys_cpu_clk /sys_ps7/S_AXI_HP2_ACLK
## ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
connect_bd_net -net /sys_cpu_resetn /axi_hp2_interconnect/S00_ARESETN
connect_bd_net -net /sys_cpu_clk /axi_hp2_interconnect/S00_ACLK
connect_bd_intf_net /axi_hp2_interconnect/S00_AXI /axi_ad9361_dac_dma/m_src_axi
connect_bd_net -net /sys_cpu_clk /axi_ad9361_dac_dma/m_src_axi_aclk
</sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into </axi_ad9361_dac_dma/m_src_axi> at <0x00000000 [ 512M ]>
## ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
connect_bd_net -net /sys_cpu_resetn /axi_ad9361_adc_dma/m_dest_axi_aresetn
## ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
connect_bd_net -net /sys_cpu_resetn /axi_ad9361_dac_dma/m_src_axi_aresetn
## ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq
delete_bd_objs /ps_intr_13_1 /ps_intr_13
connect_bd_net /sys_concat_intc/In13 /axi_ad9361_adc_dma/irq
## ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
delete_bd_objs /ps_intr_12_1 /ps_intr_12
connect_bd_net /sys_concat_intc/In12 /axi_ad9361_dac_dma/irq
create_bd_cell: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1484.750 ; gain = 36.004
## set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
## set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
## set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
## set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
## set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc
## set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
## set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
## set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
## set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
## set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_adc
## ad_connect util_ad9361_adc_fifo/dout_data_0 ila_adc/probe0
connect_bd_net /util_ad9361_adc_fifo/dout_data_0 /ila_adc/probe0
## ad_connect util_ad9361_adc_fifo/dout_data_1 ila_adc/probe1
connect_bd_net /util_ad9361_adc_fifo/dout_data_1 /ila_adc/probe1
## ad_connect util_ad9361_adc_fifo/dout_data_2 ila_adc/probe2
connect_bd_net /util_ad9361_adc_fifo/dout_data_2 /ila_adc/probe2
## ad_connect util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3
connect_bd_net /util_ad9361_adc_fifo/dout_data_3 /ila_adc/probe3
## ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4
connect_bd_net /util_ad9361_adc_fifo/dout_valid_0 /ila_adc/probe4
## ad_connect sys_cpu_clk ila_adc/clk
connect_bd_net -net /sys_cpu_clk /ila_adc/clk
## set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tdd]
## set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd
## set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd
## set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd
## set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_tdd
## set_property -dict [list CONFIG.C_PROBE0_WIDTH {42}] $ila_tdd
## ad_connect axi_ad9361_clk ila_tdd/clk
connect_bd_net -net /axi_ad9361_clk /ila_tdd/clk
## ad_connect axi_ad9361/tdd_dbg ila_tdd/probe0
connect_bd_net /axi_ad9361/tdd_dbg /ila_tdd/probe0
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_i0]]]
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_i0]]]
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_q0]]]
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_q0]]]
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_i1]]]
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_i1]]]
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_q1]]]
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_q1]]]
# delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_dunf]]]
# set axi_xcomm2ip [create_bd_cell -type ip -vlnv analog.com:user:axi_xcomm2ip:1.0 axi_xcomm2ip]
# set_property -dict [list CONFIG.XCOMM2IP_1T1R_OR_2T2R_N {0}] $axi_xcomm2ip
# ad_cpu_interconnect 0x79040000 axi_xcomm2ip
connect_bd_net -net /sys_cpu_clk /axi_cpu_interconnect/M10_ACLK
connect_bd_net -net /sys_cpu_clk /axi_xcomm2ip/s_axi_aclk
connect_bd_net -net /sys_cpu_resetn /axi_cpu_interconnect/M10_ARESETN
connect_bd_net -net /sys_cpu_resetn /axi_xcomm2ip/s_axi_aresetn
connect_bd_intf_net /axi_cpu_interconnect/M10_AXI /axi_xcomm2ip/s_axi
# ad_connect axi_ad9361/clk axi_xcomm2ip/clk
connect_bd_net /axi_ad9361/clk /axi_xcomm2ip/clk
# ad_connect axi_ad9361/rst axi_xcomm2ip/rst
connect_bd_net /axi_ad9361/rst /axi_xcomm2ip/rst
# ad_connect axi_ad9361/adc_valid_i0 axi_xcomm2ip/adc_valid_i0
connect_bd_net /axi_ad9361/adc_valid_i0 /axi_xcomm2ip/adc_valid_i0
# ad_connect axi_ad9361/adc_data_i0 axi_xcomm2ip/adc_data_i0
connect_bd_net /axi_ad9361/adc_data_i0 /axi_xcomm2ip/adc_data_i0
# ad_connect axi_ad9361/adc_valid_q0 axi_xcomm2ip/adc_valid_q0
connect_bd_net /axi_ad9361/adc_valid_q0 /axi_xcomm2ip/adc_valid_q0
# ad_connect axi_ad9361/adc_data_q0 axi_xcomm2ip/adc_data_q0
connect_bd_net /axi_ad9361/adc_data_q0 /axi_xcomm2ip/adc_data_q0
# ad_connect axi_ad9361/adc_valid_i1 axi_xcomm2ip/adc_valid_i1
connect_bd_net /axi_ad9361/adc_valid_i1 /axi_xcomm2ip/adc_valid_i1
# ad_connect axi_ad9361/adc_data_i1 axi_xcomm2ip/adc_data_i1
connect_bd_net /axi_ad9361/adc_data_i1 /axi_xcomm2ip/adc_data_i1
# ad_connect axi_ad9361/adc_valid_q1 axi_xcomm2ip/adc_valid_q1
connect_bd_net /axi_ad9361/adc_valid_q1 /axi_xcomm2ip/adc_valid_q1
# ad_connect axi_ad9361/adc_data_q1 axi_xcomm2ip/adc_data_q1
connect_bd_net /axi_ad9361/adc_data_q1 /axi_xcomm2ip/adc_data_q1
# ad_connect axi_xcomm2ip/dac_valid_i0 axi_ad9361/dac_valid_i0
connect_bd_net /axi_xcomm2ip/dac_valid_i0 /axi_ad9361/dac_valid_i0
# ad_connect axi_xcomm2ip/dac_data_i0 axi_ad9361/dac_data_i0
connect_bd_net /axi_xcomm2ip/dac_data_i0 /axi_ad9361/dac_data_i0
# ad_connect axi_xcomm2ip/dac_valid_q0 axi_ad9361/dac_valid_q0
connect_bd_net /axi_xcomm2ip/dac_valid_q0 /axi_ad9361/dac_valid_q0
# ad_connect axi_xcomm2ip/dac_data_q0 axi_ad9361/dac_data_q0
connect_bd_net /axi_xcomm2ip/dac_data_q0 /axi_ad9361/dac_data_q0
# ad_connect axi_xcomm2ip/dac_valid_i1 axi_ad9361/dac_valid_i1
connect_bd_net /axi_xcomm2ip/dac_valid_i1 /axi_ad9361/dac_valid_i1
# ad_connect axi_xcomm2ip/dac_data_i1 axi_ad9361/dac_data_i1
connect_bd_net /axi_xcomm2ip/dac_data_i1 /axi_ad9361/dac_data_i1
# ad_connect axi_xcomm2ip/dac_valid_q1 axi_ad9361/dac_valid_q1
connect_bd_net /axi_xcomm2ip/dac_valid_q1 /axi_ad9361/dac_valid_q1
# ad_connect axi_xcomm2ip/dac_data_q1 axi_ad9361/dac_data_q1
connect_bd_net /axi_xcomm2ip/dac_data_q1 /axi_ad9361/dac_data_q1
# ad_connect axi_xcomm2ip/dac_dovf axi_ad9361/dac_dovf
connect_bd_net /axi_xcomm2ip/dac_dovf /axi_ad9361/dac_dovf
# ad_connect axi_xcomm2ip/dac_dunf axi_ad9361/dac_dunf
connect_bd_net /axi_xcomm2ip/dac_dunf /axi_ad9361/dac_dunf
# ad_connect util_ad9361_dac_upack/dac_data_0 axi_xcomm2ip/dma_data_i0
connect_bd_net /util_ad9361_dac_upack/dac_data_0 /axi_xcomm2ip/dma_data_i0
# ad_connect util_ad9361_dac_upack/dac_data_1 axi_xcomm2ip/dma_data_q0
connect_bd_net /util_ad9361_dac_upack/dac_data_1 /axi_xcomm2ip/dma_data_q0
# ad_connect util_ad9361_dac_upack/dac_data_2 axi_xcomm2ip/dma_data_i1
connect_bd_net /util_ad9361_dac_upack/dac_data_2 /axi_xcomm2ip/dma_data_i1
# ad_connect util_ad9361_dac_upack/dac_data_3 axi_xcomm2ip/dma_data_q1
connect_bd_net /util_ad9361_dac_upack/dac_data_3 /axi_xcomm2ip/dma_data_q1
# ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_xcomm2ip/dma_dunf
connect_bd_net /axi_ad9361_dac_dma/fifo_rd_underflow /axi_xcomm2ip/dma_dunf
WARNING: [BD 41-1306] The connection to interface pin /axi_ad9361_dac_dma/fifo_rd_underflow is being overridden by the user. This pin will not be connected as a part of interface connection fifo_rd
# ad_connect axi_xcomm2ip/dma_dovf GND
create_bd_cell(xlconstant) size(1) value(0) name(axi_xcomm2ip_dma_dovf_GND)
connect_bd_net axi_xcomm2ip_dma_dovf_GND/dout axi_xcomm2ip/dma_dovf
# delete_bd_objs [get_bd_cells ila_adc]
# delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
# regenerate_bd_layout
# save_bd_design
Wrote : <d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/system.bd>
# validate_bd_design
WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream
WARNING: [#UNDEF] When using EMIO pins for SPI_1 tie SSIN High in the PL bitstream
# generate_target {synthesis implementation} [get_files zed.srcs/sources_1/bd/system/system.bd]
INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote : <d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/system.bd>
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_sys_ps7_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_ps7 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_iic_main_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_axi_iic_main_0'...
INFO: [IP_Flow 19-1706] Not generating 'Implementation' target for IP 'system_axi_iic_main_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_main .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_sys_i2c_mixer_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_i2c_mixer .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_sys_concat_intc_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_concat_intc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_sys_rstgen_0'...
INFO: [Device 21-403] Loading part xc7z020clg484-1
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_sys_rstgen_0'...
INFO: [IP_Flow 19-1706] Not generating 'Implementation' target for IP 'system_sys_rstgen_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_rstgen .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_sys_logic_inv_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_logic_inv .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_hdmi_clkgen_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_clkgen .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_hdmi_core_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_core .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_hdmi_dma_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hdmi_dma .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_sys_audio_clkgen_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_sys_audio_clkgen_0'...
INFO: [IP_Flow 19-1706] Not generating 'Implementation' target for IP 'system_sys_audio_clkgen_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block sys_audio_clkgen .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_spdif_tx_core_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_spdif_tx_core .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_i2s_adi_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_i2s_adi .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_iic_fmc_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_axi_iic_fmc_0'...
INFO: [IP_Flow 19-1706] Not generating 'Implementation' target for IP 'system_axi_iic_fmc_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_fmc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_xbar_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/xbar .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_ad9361_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361 .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_ad9361_dac_dma_0'...
WARNING: [IP_Flow 19-1971] File named "../../ipshared/analog.com/common/sync_bits.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_axi_ad9361_dac_dma_0'...
INFO: [IP_Flow 19-1706] Not generating 'Implementation' target for IP 'system_axi_ad9361_dac_dma_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_dac_dma .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ad9361_dac_upack_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_dac_upack .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_ad9361_adc_dma_0'...
WARNING: [IP_Flow 19-1971] File named "../../ipshared/analog.com/common/sync_bits.v" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'system_axi_ad9361_adc_dma_0'...
INFO: [IP_Flow 19-1706] Not generating 'Implementation' target for IP 'system_axi_ad9361_adc_dma_0'. Target already exists and is up to date.
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_ad9361_adc_dma .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ad9361_adc_pack_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_pack .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ad9361_adc_fifo_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_adc_fifo .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_util_ad9361_tdd_sync_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ad9361_tdd_sync .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_xcomm2ip_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_xcomm2ip .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_axi_xcomm2ip_dma_dovf_GND_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_xcomm2ip_dma_dovf_GND .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_pc_0'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_cpu_interconnect/s00_couplers/auto_pc .
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'system_auto_pc_1'...
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_hp0_interconnect/s00_couplers/auto_pc .
Exporting to file d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/hw_handoff/system.hwh
Generated Block Design Tcl file d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
Generated Hardware Definition File d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/hdl/system.hwdef
generate_target: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1560.594 ; gain = 42.848
# make_wrapper -files [get_files zed.srcs/sources_1/bd/system/system.bd] -top
# import_files -force -norecurse -fileset sources_1 zed.srcs/sources_1/bd/system/hdl/system_wrapper.v
# adi_project_files zed [list \
# "D:/DCP/rfbbp/hdl/library/common/ad_iobuf.v" \
# "D:/DCP/rfbbp/hdl/projects/fmcomms2/zed/system_top.v" \
# "D:/DCP/rfbbp/hdl/projects/fmcomms2/zed/system_constr.xdc"\
# "D:/DCP/rfbbp/hdl/projects/common/zed/zed_system_constr.xdc" ]
# adi_project_run zed
[Sat Oct 08 17:48:11 2016] Launched synth_1...
Run output will be captured here: d:/DCP/rfbbp/zed/zed.runs/synth_1/runme.log
[Sat Oct 08 17:48:12 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:48:17 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:48:22 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:48:27 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:48:37 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:48:47 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:48:57 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:49:07 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:49:27 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:49:47 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:50:07 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:50:27 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:51:07 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:51:47 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:52:27 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:53:07 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:54:27 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:55:47 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:57:07 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:58:27 2016] Waiting for synth_1 to finish...
[Sat Oct 08 17:58:40 2016] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:10 ; elapsed = 00:10:29 . Memory (MB): peak = 1560.594 ; gain = 0.000
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7z020clg484-1
INFO: [Netlist 29-17] Analyzing 1395 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.4.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc] for cell 'i_system_wrapper/system_i/sys_ps7/inst'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_ps7_0/system_sys_ps7_0.xdc] for cell 'i_system_wrapper/system_i/sys_ps7/inst'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_main'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_iic_main_0/system_axi_iic_main_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_main'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_rstgen_0/system_sys_rstgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_rstgen'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/U0'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/U0'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0_board.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc:56]
INFO: [Timing 38-2] Deriving generated clocks [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc:56]
get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 2161.453 ; gain = 475.789
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_sys_audio_clkgen_0/system_sys_audio_clkgen_0.xdc] for cell 'i_system_wrapper/system_i/sys_audio_clkgen/inst'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_iic_fmc_0/system_axi_iic_fmc_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_fmc'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_iic_fmc_0/system_axi_iic_fmc_0_board.xdc] for cell 'i_system_wrapper/system_i/axi_iic_fmc'
Parsing XDC File [D:/DCP/rfbbp/hdl/projects/fmcomms2/zed/system_constr.xdc]
Finished Parsing XDC File [D:/DCP/rfbbp/hdl/projects/fmcomms2/zed/system_constr.xdc]
Parsing XDC File [D:/DCP/rfbbp/hdl/projects/common/zed/zed_system_constr.xdc]
Finished Parsing XDC File [D:/DCP/rfbbp/hdl/projects/common/zed/zed_system_constr.xdc]
Sourcing Tcl File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ipshared/analog.com/axi_dmac_v1_0/bd/bd.tcl]
Finished Sourcing Tcl File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ipshared/analog.com/axi_dmac_v1_0/bd/bd.tcl]
Sourcing Tcl File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ipshared/analog.com/axi_dmac_v1_0/bd/bd.tcl]
Finished Sourcing Tcl File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ipshared/analog.com/axi_dmac_v1_0/bd/bd.tcl]
Parsing XDC File [d:/DCP/rfbbp/zc706/.Xil/Vivado-4308-yu-qiyun/dcp/system_top.xdc]
Finished Parsing XDC File [d:/DCP/rfbbp/zc706/.Xil/Vivado-4308-yu-qiyun/dcp/system_top.xdc]
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_hdmi_clkgen_0/axi_clkgen_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_clkgen'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_hdmi_clkgen_0/axi_clkgen_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_clkgen'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/axi_hdmi_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_hdmi_core_0/axi_hdmi_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/common/ad_axi_ip_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/common/ad_axi_ip_constr.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_core'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0_clocks.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/U0'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_hdmi_dma_0/system_axi_hdmi_dma_0_clocks.xdc] for cell 'i_system_wrapper/system_i/axi_hdmi_dma/U0'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/axi_spdif_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_spdif_tx_core'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_spdif_tx_core_0/axi_spdif_tx_constr.xdc] for cell 'i_system_wrapper/system_i/axi_spdif_tx_core'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc] for cell 'i_system_wrapper/system_i/axi_i2s_adi'
INFO: [Timing 38-2] Deriving generated clocks [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc:1]
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_i2s_adi_0/axi_i2s_adi_constr.xdc] for cell 'i_system_wrapper/system_i/axi_i2s_adi'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_ad9361_0/axi_ad9361_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/common/ad_axi_ip_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/common/ad_axi_ip_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_dma'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_ad9361_dac_dma_0/system_axi_ad9361_dac_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_dac_dma'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_util_ad9361_dac_upack_0/util_upack_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_dac_upack'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_util_ad9361_dac_upack_0/util_upack_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_dac_upack'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_adc_dma'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_ad9361_adc_dma_0/system_axi_ad9361_adc_dma_0_constr.xdc] for cell 'i_system_wrapper/system_i/axi_ad9361_adc_dma'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_pack_0/util_cpack_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_pack'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_pack_0/util_cpack_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_pack'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_fifo'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_util_ad9361_adc_fifo_0/util_wfifo_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_adc_fifo'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_tdd_sync'
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_util_ad9361_tdd_sync_0/util_tdd_sync_constr.xdc] for cell 'i_system_wrapper/system_i/util_ad9361_tdd_sync'
Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_xcomm2ip_0/axi_xcomm2ip_constr.xdc] for cell 'i_system_wrapper/system_i/axi_xcomm2ip'
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {name =~ *s_dac_ack_t_reg && IS_SEQUENTIAL}'. [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_xcomm2ip_0/axi_xcomm2ip_constr.xdc:13]
CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-from [get_cells -hier -filter {name =~ *s_dac_ack_t_reg && IS_SEQUENTIAL}]'. [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_xcomm2ip_0/axi_xcomm2ip_constr.xdc:13]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-180] No cells matched 'get_cells -hier -filter {name =~ *s_adc_ack_t_reg && IS_SEQUENTIAL}'. [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_xcomm2ip_0/axi_xcomm2ip_constr.xdc:14]
CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-from [get_cells -hier -filter {name =~ *s_adc_ack_t_reg && IS_SEQUENTIAL}]'. [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_xcomm2ip_0/axi_xcomm2ip_constr.xdc:14]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ip/system_axi_xcomm2ip_0/axi_xcomm2ip_constr.xdc] for cell 'i_system_wrapper/system_i/axi_xcomm2ip'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_e_reg has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_e_reg cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_e_reg has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_e_reg cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[0] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[0] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[0] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[0] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[1] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[1] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[1] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[1] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[2] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[2] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[2] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[2] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[3] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[3] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[3] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[3] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[4] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[4] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[4] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[4] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[5] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[5] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[5] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[5] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[6] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[6] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[6] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[6] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[7] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[7] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[7] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[7] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[8] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[8] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[8] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[8] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[9] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[9] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[9] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[9] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[10] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[10] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[10] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[10] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[11] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[11] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[11] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[11] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[12] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[12] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[12] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[12] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[13] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[13] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[13] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[13] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[14] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[14] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[14] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[14] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[15] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[15] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
WARNING: [Shape Builder 18-132] Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[15] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance i_system_wrapper/system_i/axi_hdmi_core/inst/i_tx_core/hdmi_16_data_reg[15] cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site.
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'axi_xcomm2ip_core' instantiated as 'i_system_wrapper/system_i/axi_xcomm2ip/inst/i_core' [d:/DCP/rfbbp/zed/zed.srcs/sources_1/bd/system/ipshared/analog.com/axi_xcomm2ip_v1_0/axi_xcomm2ip.v:645]
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 80 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 55 instances
OBUFDS => OBUFDS: 8 instances
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 16 instances
RAM32X1D => RAM32X1D (RAMD32, RAMD32): 1 instances

INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.492 . Memory (MB): peak = 2263.066 ; gain = 0.000
[Sat Oct 08 17:59:38 2016] Launched impl_1...
Run output will be captured here: d:/DCP/rfbbp/zed/zed.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 2263.066 ; gain = 0.000
[Sat Oct 08 17:59:38 2016] Waiting for impl_1 to finish...
[Sat Oct 08 17:59:43 2016] Waiting for impl_1 to finish...
[Sat Oct 08 17:59:48 2016] Waiting for impl_1 to finish...
[Sat Oct 08 17:59:53 2016] Waiting for impl_1 to finish...
[Sat Oct 08 18:00:03 2016] Waiting for impl_1 to finish...
[Sat Oct 08 18:00:13 2016] Waiting for impl_1 to finish...
[Sat Oct 08 18:00:18 2016] impl_1 finished
wait_on_run: Time (s): cpu = 00:00:02 ; elapsed = 00:00:40 . Memory (MB): peak = 2263.066 ; gain = 0.000
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
update_compile_order -fileset sim_1

 

Thank you very much for your help!!!

Qiyun

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