I am debugging the ad9361 with FMCOMMS2 and the baseband platform is zedboard.
I have verified the board with local vcxo on the board successfully.
Now i have to synchronized the board with the signal source equipment,so i used an external reference clock offered by the signal source equipment.I have changed the initialization configuration to adpat the change, and the frequnecy of the clock input is 10MHz with Vp-p ~=1.3V.
But the phase loop part is not locked,which is verified by query registers 0x05E(Baseband PLL),0x247(Rx PLL),0x287(Tx PLL).
Could somebody give some suggestions? I can do the test quickly.