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Configuring phase relationship between two outputs of HMC7044 with Analog fine delay feature

Question asked by DonkeyH0T on Oct 7, 2016
Latest reply on Nov 24, 2016 by kpeker

Hello!

I have some questions about the HMC7044. In my application i need to have 2 different clocks of 3 GHz and 1.5 GHz. Also i want to have the opportunity of changing phase relationship between this clocks. Datasheet for HMC7044 says (page  9) that "Maximum Analog Fine Delay Frequency 1600 MHz" So, i want to know what does this "Maximum Analog Fine Delay Frequency" mean. Is it the maximum frequency of the internal VCO of PLL2? Or may be it is the frequency after the divider before coarse digital delay and analog delay?

I want to setup frequency of the internal VCO of PLL2 to 3GHz and bypass it to CLOCKOUT0. Also i want to generate clock of 1.5 GHz by dividing VCO frequency by 2 and delay it via analog delay circuit of CLOCKOUT2.

Is it possible? Are phase relation between two output clocks  fixed? When i adjust analog delay of CLOCKOUT2 by 1 step of 25 ps it means that CLOCKOUT2 is delayed relatively to CLOCKOUT0?

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