Output impedance for bias voltage (Vbias) generator is not specified in the datasheet for AD7124-4. Could you specify the typical value ?
Do you require this information on the output impedance because you are driving resistive loads ? The bias circuitry was designed for capacitive loads (eg thermocouples). Output impedance is 8k approximately. Below is a simulation plot showing output voltage vs Rload. The x-axis is load resistance in Meg Ohms so span is from 10k to 1Meg. Y axis is voltage from Vbias in volts. With a large resistive load, output is Vdd/2 (1.5V) and drops off with smaller load.
The bias voltage generator is used to bias the negative terminal of the selected input channel to (AVDD - AVSS)/2 and the output impedance is not needed for this since it tends to keep the voltage at it source value no matter what the load. However, the power-up time of the bias voltage generator is dependent on the load capacitance, it has a typical value of 6.7 us/nF.
Jellenie, output impedance is needed if the bias voltage generator will be loaded by some external load.
However, the power-up time of the bias voltage generator is dependent on the load capacitance, it has a typical value of 6.7 us/nF
I have seen this specification in the datasheet, but I need output impedance for considering external dc-loading. Not for transient power-up.
Many of compatible ADCs have this specification (output impedance), for example:
I'll try to check this with the product owner and get back to you with an answer.
Do you require this information on the output impedance because you are driving resistive loads ?
Yes, I would like to consider this approach to provide a run-time calibration of the high-resistance voltage divider in front of AD7124-4 (divider ratio, not absolute value). The approach consists of the 3 steps and shown below (at the moment of writing it was not designed and tested):
"Red components" - whose influence should be taken into account when using the calibration (expected, not verified)
"Blue components" are not included into the calibration (their influence remains unaccounted).
Output impedance of Vbias has to be in several kOhm range to provide a current return path for ~ 1uA excitation current.
How do you think is this approach (calibration of divider ratio) is a reasonable approach ?
P.S. External divider is for measurement of voltages up to 10V
Hi Mary, I've been set up the question as "solved", but I would like to continue discussion of the suggested approach for run-time calibration of the external resistor divider ratio. Do I need to create a special topic or we can continue here ?
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