I have some questions about the HMC7044.
I will have a 10MHz reference input frequency and a 100MHz VCXO. My output frequencies will be a 3GHz ADC sample clock and a 10MHz SYSREF clock.
I will be making use of the SYNC input pin and I have some questions about the configuration of the SYNC pin (Table 58 in the datasheet):
1) SYNC polarity: does this bit only control the polarity when using RFSYNCIN/RFSYNCIN#? I am only using SYNC so should I set this to '0'?
2) SYNC through PLL2: I understand from the datasheet that if a SYNC event is detected then the FSM propagates the synchronisation through PLL2 to the output drivers. What does this bit refer to?
3) SYNC retime: I will be generating the SYNC input signal with adequate setup and hold time relative to the 100MHz VCXO frequency. What retiming function does this bit refer to? Does the HMC7044 offer the option to retime the SYNC input relative to the reference input clock (10MHz in my case)?
Looking forward to understanding this better!