Using SS with SC589 board. Created two projects with 2 channels of FIR filtering (948 and 1024 tap each, the weird size is from using an actual filter that wasn't padded with 0s).
One schematic uses the normal FIR block, and shows about 54 MIPS when running, which seems reasonable. The one based on using the FIR accelerator hardware (copy attached) shows around 233 MIPS, almost 4 times the load. Seems like it should be close to the load of a minimal in to out design, a few MIPS?
1) Why is the load so high? Is it an error in the MIPS calc or is the library doing something wrong?
2) In a more complex system will the SHARC core execute functions while waiting for the FIR accelerator to finish? (the simple example I created has nothing else to do but wait)