I'm working with an ADF4355-2 PLL and I am experiencing some problems with locking. I am using the PLL on a custom board that I designed. The reference is a 100MHz differential ECL clock, and I want to obtain a 1.3GHz output signal, but the PLL does not lock properly: at the output I can see a 1306 MHz sine wave (plus its second harmonic). The output of the R divider is correct (50MHz in this case), while the output of the N divider is unexpected (I can see a 100kHz signal). The tuning voltage is saturated at Vvco-0.4v (4.6v). I've tried two different loop filters (the one in the data sheet and one designed by ADIsimPLL), but nothing changes. I'm using these settings:
I will appreciate all suggestions and hints. Thank you.