I was wondering if there was a way to trigger an AUXADC sampling from the state machine. For example, I pull the TXNRX line high, and after a programmed delay the ADC samples its input and stores the value in the register.
There no way to trigger the sampling of AUXADC from state machine, but in your FPGA you can implement a logic to sample voltage on AUXADC i/p after a delay from TXNRX line goes high.
Sampling of voltage is explained in UG-570 page 83
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