On the ADN2815, what is the delay between the input pins PIN/NIN and the output pins DATAOUTP/DATAOUTN?
Is this delay fixed and what is the part to part skew ?
AD8015 was designed to support OC3 or lower rates telecommunication applications.
What is your target applications?
Thank you for your response. My application is not a standard telecommunication applications. I am trying to design serial data links running at moderate speed, between 100 Mbps to a few hundred Mbps, that exhibit simultaneously three properties: a fixed, a low and a predictable latency between one sender and multiple receivers.
In general, our requirements can be of the order of several hundreds of ns of for the serailization, transmission over a few meters, and deserialization delays, up to several ns of skew beetween two identically built receivers, and a typical jitter of less than approximately 100 ps. But for the most demanding applications, the tolerable dispersion of skew and jitter are less, e.g. better than 100 ps alignement skew between the recovered clock of two independant receivers and <20 ps recovered clock jitter. For the data, the alignment required between two receivers is always one bit. It cannot be less, but it must not be more, unless the skew between two receivers is known and we can compensate it with a shift register in the receiver logic for example.
This is why I would like to know the propagation delay of the encoded data stream from the input to the output of the ADN2815, and understand more on the properties of this delay.
Because serial data capture will be made with the recovered clock, I also need to know what is the phase of the recovered clock compared to the encoded input stream (normally it should be half a unit-interval to sample serial data at the optimum time), to which extent this delay is constant or variable, and what its jitter is.
Thanks for info and advice,
Sorry for the confusion I made early. AD8015 is one TIA product. You are interested in ADN2815, a CDR product.
ADN2815 uses one proprietary Dual Loop Controls to lock in input data quickly, and maintain signal lock (after locked to input signal) with superior jitter performance. Due to its complex internal circuitry response, the PIN/NIN to DATAOUTP/N setup (propagation) time could vary, depends on the input signal data rate, input signal integrity, system noise, and environment.
Please contact our local sales team (with your application requirement details) to get necessary applications support, if you decide to evaluate this device.
Retrieving data ...