Recently I have been working with AD9361 and so far I've been impressed with the speed and flexibility that it offers. Presently, I'm evaluating the performance of this SDR on fmcomms4 with Zed board using the No-OS software provided by ADI for fast scan applications. From the data sheet it seems that the lock times for changing Rx LO is around 250 us for the worst case and 20 us for the best case. However, I don't seem to get anywhere near this performance at all. Here's what I did :
Wrote a small for loop in which I continuously try to change/increase Rx LO frequency by a step size of +40 MHz using the ADI provided API ad9361_set_rx_lo_freq(). I used some trivial method (a stop watch) to calculate the amount of time it takes to change LO frequencies 10000 times and from this it turned out that the time per execution of ad9361_set_rx_lo_freq() API itself is ~2.5 ms per iteration (25 s for 10000 iterations). This is nowhere close to what ADI claims in their data sheet. On using profiling tools provided by Xilinx SDK I found out that some API called SPI_PolledTransfer() (don't exactly remember the name) is consuming 70% of the execution times. Please note that during the test, there were no interrupts active on the system and console commands/console prints were all commented or turned off.
So, could someone please confirm if this is an expected behaviour ? Or am I doing anything wrong ? Os is there any way to get close to the lock time of 250 us ?