AD9652 ADC switching specifications are:
DCO±-to-Data Skew (tSKEW) Typical 0 ns
(see datasheet Rev. A on page 7)
Which is the min and max value?
I've to interface this ADC device with device with an FPGA at 307.2 MHz clock rate so I need the min/max tSKEW in order to make sure the interface timing are proper.