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Which clock does ADC/DACs use in ADAU1361?

Question asked by srinie on Sep 28, 2016
Latest reply on Sep 28, 2016 by DaveThib


I am using ADAU1361 with the "codec in PLL mode + codec as I2S Slave".


In our system, we wish to tune the ADCs/DACs based on the I2S SCK,LRCK variations.

As the codec is configured in I2S slave mode, we expect (or understand) that any modifications in SCK,LRCK result in corresponding ADC/DAC clock changes.


But in the test setup, we observe frequent audio clicks with the above configuration!

Does this imply that irrespective of SCK,LRCK changes (when in Slave), ADC/DAC always work using PLL clock?