I am using ADAU1361 with the "codec in PLL mode + codec as I2S Slave".
In our system, we wish to tune the ADCs/DACs based on the I2S SCK,LRCK variations.
As the codec is configured in I2S slave mode, we expect (or understand) that any modifications in SCK,LRCK result in corresponding ADC/DAC clock changes.
But in the test setup, we observe frequent audio clicks with the above configuration!
Does this imply that irrespective of SCK,LRCK changes (when in Slave), ADC/DAC always work using PLL clock?