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dds synchronization

Question asked by jpotter0 on Sep 28, 2016
Latest reply on Oct 10, 2016 by JLKeip

I am working on a project that need synchronized sources that are not necessarily close together.At present we are using AD9959 chips. Our application is for a linear accelerator system with multiple accelerator sections each with its own klystron power source. The required phase is determined through a tuneup procedure to compensate for system phase shifts and beam dynamics requirements. We need only to insure that the phase relations stay the same so that the complex tune up procedure doesn't need to be executed every time the system is turned on.


We find that the published synchronization scheme is complex to implement in our system. We propose to use a different procedure. The reference clock will be distributed with a clock fanout, such as the AD9508. The procedure we plan to use is to turn the reference clock of, reset all devices, send data to the input registers, assert IO_UPDATE, turn the rf clock on (the 9508 insures a full pulse at the start), and then issue a synchronized end to the IO_UPDATE pulse. This should load the internal registers in all chips at the same time, synchronizing the units. We are planning to use an FPGA with each DDS chip for control. One idea we have is to avoid sending an accurately timed IO_UPDATE pulse to each unit is to divide down the reference clock to a frequency that the FPGA can count. The let the FPGA reset the IO_UPDATE at each unit simultaneously by counting the divided down reference clock. In this case our reference clock is near 500 MHz.


From studying the AD9959 data sheet we believe this scheme will work. We are still a week or two away from testing it.


Our desired output frequency is 2998.5 MHz. To achieve that in a synchronized way we are using a heterodyne scheme where both input signals to an up converter are derived from the DDS. One channel has a signal at 370 MHz that is filtered and amplified to +17 dBm to drive the upconverter. We are using it as a "subharmonic upconverter" That is the adjustable phase and amplitude signal at 408.5 MHz is mixed with the 7th harmonic of 370 MHz. The resulting output is high enough amplitude that we get an acceptable SNR. The output level is 40 mW peak. (Ttis is a pulsed system, 10 us @ 240 Hz.) We are using four level AM to generate OFF, Ampl1, Ampl2, Ampl3, within the 10 us interval.


I invite comments on our sync scheme, but my question is ultimately about the AD9915. We have recently discovered the existence of this chip and have purchased an Eval board. With this chip we would generate the 2998.5 MHz signal directly, programming the frequency to 2998.5 (not 2001.5) and using the first image. I have tested that scheme and it works well using a 2500 MHz clock. I have also looked at using the internal PLL with a 125 MHz reference input. That appears to yield a signal with more nose on it. My interpretation of the frequency spectrum is that there will be 0.6% amplitude fluctuations from pulse-to-pulse. This may be acceptable, but that's not the big issue.


The big issue with the 9915 is the requirement for a DAC calibration after a  Power Up. It is not clear from the documentation whether or not a DAC calibration is required after a chip reset. The software provided for the Eval board wants me to do a DAC reset, but experimentally I find that if I ignore it and simply reload the registers everything seems to be fine. I don't think our gated reference sync scheme will work if  a DAC calibration is required after a reset.


To sum it all up, my question boils down to: does the reset change whatever registers are set in the DAC calibration?