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SMC access abnormal sequence on Griffin

Question asked by robin.hu Employee on Sep 28, 2016
Latest reply on Oct 7, 2016 by nithya.koch

On Griffin board, SMC was used to access the memory in FPGA, with logic analyzer we found the order of write/read access was unexpectedly changed and thus inconsistent with the sequence of code in program.

More details please check the attached files and test project.

Please try to help explain this abnormal test result.

============================================

Issue Case#1

  1. TestCode

uint32_t i;

*pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN

                                                | ENUM_SMPU_SECURECTL_WNSDIS

                                                | ENUM_SMPU_SECURECTL_RSECEN

                                                | ENUM_SMPU_SECURECTL_RNSDIS

                                                | ENUM_SMPU_SECURECTL_SBEDIS);

 

SMC_Bank_Config(1, SMC_BCTL_VALUE,SMC_BTIM_VALUE,SMC_BETIM_VALUE);

 

*pREG_SPU0_SECUREP48=0x3;

 

while(1)

              {

                     *(SMC_LinkPort)=0xaaaa;

                     *(SMC_LinkPort+0x5555)=0x5555;

                     *(SMC_LinkPort+0xaaaa)=0x55aa;

                     read_data1[0]=*(SMC_LinkPort+0x1000);

                     read_data1[1]=*(SMC_LinkPort+0x2000);

                     read_data1[2]=*(SMC_LinkPort+0x3000);

                     for(i=0;i<500;i++)

                     {

                           ;

                     }

              }

  1. Test Result

With Logic Analyzer to capture the SMC access from the beginning of loops.

(1) First loop(see following pic#1):

It has abnormal access sequence (expected to be 3 writes follows with 3 reads):

       2 writes==>1 read==>1 write==>2 reads

   2 Writes:    

     *(SMC_LinkPort)=0xaaaa

     *(SMC_LinkPort+0x5555)=0x5555

1 Reads:

         read_data1[0]=*(SMC_LinkPort+0x1000)

   1 Writes:    

        *(SMC_LinkPort+0xaaaa)=0x55aa

   2 Reads

       read_data1[1]=*(SMC_LinkPort+0x2000)

         read_data1[2]=*(SMC_LinkPort+0x3000);

(2) 2nd loop(see following pic#2):

   Same error as 1st loop.

(3) 3rd loop(see following pic#3):

It has abnormal access sequence (expected to be 3 writes follows with 3 reads):

       1 write==>1 read==>1 write==>1 read==>1 write==>1 read

     1 write:

           *(SMC_LinkPort)=0xaaaa  

     1 read:

          read_data1[0]=*(SMC_LinkPort+0x1000)

     1 write:

          *(SMC_LinkPort+0x5555)=0x5555

     1 read:

         read_data1[1]=*(SMC_LinkPort+0x2000)

   1 write

        *(SMC_LinkPort+0xaaaa)=0x55aa

     1 read:

        read_data1[2]=*(SMC_LinkPort+0x3000);

(4) >4th loops

     Same as 3rd loop

 

 

Normal Case #2

  1. Test Code

 

     uint32_t i;

       *pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN

                                                | ENUM_SMPU_SECURECTL_WNSDIS

                                                | ENUM_SMPU_SECURECTL_RSECEN

                                                | ENUM_SMPU_SECURECTL_RNSDIS

                                                | ENUM_SMPU_SECURECTL_SBEDIS);

 

              SMC_Bank_Config(1, SMC_BCTL_VALUE,SMC_BTIM_VALUE,SMC_BETIM_VALUE);

 

              *pREG_SPU0_SECUREP48=0x3;

 

              while(1)

              {

 

                     *pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN

                                                                     | ENUM_SMPU_SECURECTL_WNSDIS

                                                                     | ENUM_SMPU_SECURECTL_RSECDIS

                                                                     | ENUM_SMPU_SECURECTL_RNSDIS

                                                                     | ENUM_SMPU_SECURECTL_SBEDIS);

 

                     *(SMC_LinkPort)=0xaaaa;

                     *(SMC_LinkPort+0x5555)=0x5555;

                     *(SMC_LinkPort+0xaaaa)=0x55aa;

 

              *pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECDIS

                                                       | ENUM_SMPU_SECURECTL_WNSDIS

                                                       | ENUM_SMPU_SECURECTL_RSECEN

                                                       | ENUM_SMPU_SECURECTL_RNSDIS

                                                       | ENUM_SMPU_SECURECTL_SBEDIS);

                     read_data1[0]=*(SMC_LinkPort+0x1000);

                     read_data1[1]=*(SMC_LinkPort+0x2000);

                     read_data1[2]=*(SMC_LinkPort+0x3000);

                     //for(i=0;i<2000;i++)

                     for(i=0;i<500;i++)

                     {

                                         ;

                     }

              }

  1. Test Result

   With Logic Analyzer to capture the SMC access from the beginning of loops.

   The read/write access is as expected, ie, write 3 times then read 3 times.

 

Issue Case#3

  1. TestCode

  uint32_t i;

       *pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN

                                                | ENUM_SMPU_SECURECTL_WNSDIS

                                                | ENUM_SMPU_SECURECTL_RSECEN

                                                | ENUM_SMPU_SECURECTL_RNSDIS

                                                | ENUM_SMPU_SECURECTL_SBEDIS);

 

              SMC_Bank_Config(1, SMC_BCTL_VALUE,SMC_BTIM_VALUE,SMC_BETIM_VALUE);

 

              *pREG_SPU0_SECUREP48=0x3;

 

              while(1)

              {

 

                     *pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN

                                                                     | ENUM_SMPU_SECURECTL_WNSDIS

                                                                     | ENUM_SMPU_SECURECTL_RSECDIS

                                                                     | ENUM_SMPU_SECURECTL_RNSDIS

                                                                     | ENUM_SMPU_SECURECTL_SBEDIS);

 

                     *(SMC_LinkPort)=0xaaaa;

                     *(SMC_LinkPort+0x5555)=0x5555;

                     *(SMC_LinkPort+0xaaaa)=0x55aa;

 

              *pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECDIS

                                                       | ENUM_SMPU_SECURECTL_WNSDIS

                                                       | ENUM_SMPU_SECURECTL_RSECEN

                                                       | ENUM_SMPU_SECURECTL_RNSDIS

                                                       | ENUM_SMPU_SECURECTL_SBEDIS);

                     read_data1[0]=*(SMC_LinkPort+0x1000);

                     read_data1[1]=*(SMC_LinkPort+0x2000);

                     read_data1[2]=*(SMC_LinkPort+0x3000);

                     for(i=0;i<500;i++)

                     {

                                         ;

                     }

              }

  1. Test result

(1) place breakpoint at *pREG_SMPU0_SECURECTL = xxx code line,

(2) run to breakpoint

(3) 3 writes are as normal.

(4) step run

       *pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECDIS

                                                       | ENUM_SMPU_SECURECTL_WNSDIS

                                                       | ENUM_SMPU_SECURECTL_RSECEN

                                                       | ENUM_SMPU_SECURECTL_RNSDIS

                                                       | ENUM_SMPU_SECURECTL_SBEDIS);

   It will result unexpected 2 reads (see following pic), ie,

        read_data1[0]=*(SMC_LinkPort+0x1000)

       read_data1[1]=*(SMC_LinkPort+0x2000)

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